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468 Views
Registered: ‎01-30-2019

Post synthesis simulation not working, But Behavioral Simulation is working

Hi,

I have tried a simple verilog program to do simple methemetical operation. The simulation is working fine. When I syntheise the code it is not giving any error but in Post Syntheis functional simulation it gives errors.  Please help me to reolve the issue.

Thanks 

 

I also have pasted the code along with test bench.  

-------------------------Error Message-------------------------------------------------------------------------------------

 launch_simulation -mode post-synthesis -type functional
INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in '/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...
INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim/TB_array_func_synth.v"
INFO: [SIM-utils-36] Netlist generated:/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim/TB_array_func_synth.v
INFO: [SIM-utils-54] Inspecting design source files for 'TB_array' in fileset 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim'
xvlog --incr --relax -prj TB_array_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim/TB_array_func_synth.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module array
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/fpgauser5/Adder_test/Adder_test.srcs/sources_1/new/TB_array.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module TB_array
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /D/fpga/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto 1673f639047046e882b15a8a437398cb --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot TB_array_func_synth xil_defaultlib.TB_array xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
ERROR: [VRFC 10-426] cannot find port memu2 on this module [/home/fpgauser5/Adder_test/Adder_test.srcs/sources_1/new/TB_array.v:38]
ERROR: [VRFC 10-426] cannot find port memu1 on this module [/home/fpgauser5/Adder_test/Adder_test.srcs/sources_1/new/TB_array.v:37]
ERROR: [VRFC 10-2063] Module <OBUF> not found while processing module instance <finished_OBUF_inst> [/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim/TB_array_func_synth.v:45]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/fpgauser5/Adder_test/Adder_test.sim/sim_1/synth/func/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

------------------------------------------------------------------------------------------------------------------------------------------

 

 

------------------------------------------------code----------------------------------------------------------

----------------------Module-------------------
module array(
input wire clk,
input wire reset,
input wire [7:0] memu1[3:0],
input wire [7:0] memu2[3:0],
output reg [7:0] sum,

output reg finished

);

//input clk,reset;
//input [7:0] din;
//output reg [7:0] sum;
// reg [7:0] memu1[3:0];
// reg [7:0] memu2[3:0];
integer i=0;

always@(posedge clk)
begin
if(reset ==1)
begin
i=0;
sum=0;
finished=0;
end
else
begin
i= i+1;
end
end

//always@(posedge clk)
// begin
// if(reset==0)

// end

always@(posedge clk)

begin
if(reset ==0)
begin
if(i<5)
begin
sum = sum + (memu1[i-1]*memu2[i-1]);
end
else
finished = 1;
end
end
//end
endmodule

---------------------------------------------------------

 

-----------------Test Bench------------------------


module TB_array();

bit clk=1;
reg reset,start;
wire [7:0] sum;

reg [7:0] memu1[3:0];
reg [7:0] memu2[3:0];

wire finished;
integer a;
array array(
.clk(clk),
.reset(reset),
.memu1(memu1[3:0]),
.memu2(memu2),
.sum(sum),
.finished(finished)
);

initial
begin
for(a=1;a<5;a=a+1)
begin
memu1[a-1] = a;
memu2[a-1] = 5;
end
reset =0;
#10;
reset =1;
#10;
reset =0;
start = 1;

#100;
reset =1;
#10;
reset =0;
start = 1;
end

always
begin
#1 clk=~clk;
end

endmodule

Tags (2)
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8 Replies
Moderator
Moderator
464 Views
Registered: ‎05-31-2017

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi @piyushmanavar ,

As a first check did you see the synthesis log to find any warnings related to the trimming of the signals ? Also, you can see the synthesized schematic to find whether all the ports are present or some have got trimmed during synthesis.

 

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445 Views
Registered: ‎01-30-2019

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi Shameera,


@shameera wrote:

Hi @piyushmanavar ,

As a first check did you see the synthesis log to find any warnings related to the trimming of the signals ? Also, you can see the synthesized schematic to find whether all the ports are present or some have got trimmed during synthesis.

 


I found the many components have been trimmed, but no clue in synthesis log (Pasted at the last).

But before this code (the same that i have pasted in forst post) I have tried another similar code (pasted below) and the result (error messeges) was same except sysnthesizes circuit. 

With the code (first post) : The synthesized circuit is trimmed.

With this new code (pasted below): Circuits is generated as expected without trimming. But in post synthesis functional simulation fails with same error.

My main aim in this exercise is to use port array using verilog/sytemverilog in vivado. Also expect the code should be synthesiz

 

----------------------------------code------------------------------------------

 

module array(
input wire clk,
input wire reset,

output reg [7:0]sum

);

//input clk,reset;
//input [7:0] din;
//output reg [7:0] sum;
reg [7:0] memu1[3:0];
reg [7:0] memu2[3:0];
integer i;

always@(posedge clk)
begin
if(reset==1'b1)
begin
memu1[0]=1;
memu1[1]=2;
memu1[2]=3;
memu1[3]=4;
memu2[0]=5;
memu2[1]=5;
memu2[2]=5;
memu2[3]=5;
sum=0;
end
else
begin
sum=0;
for(i=0;i<4;i=i+1)
begin
if(i<4)
begin
sum = sum + (memu1[i]*memu2[i]);
end
end
end
end
endmodule

-----------------------------------------------------------------------------------------------------------

 

 

 

---------------------------------------Synthesis log---------------------------------------------------

#-----------------------------------------------------------
# Vivado v2018.2.2 (64-bit)
# SW Build 2348494 on Mon Oct 1 18:25:39 MDT 2018
# IP Build 2318053 on Mon Oct 1 21:44:26 MDT 2018
# Start of session at: Fri Mar 15 07:53:33 2019
# Process ID: 47590
# Current directory: /home/fpgauser5/Adder_test/Adder_test.runs/synth_1
# Command line: vivado -log array.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source array.tcl
# Log file: /home/fpgauser5/Adder_test/Adder_test.runs/synth_1/array.vds
# Journal file: /home/fpgauser5/Adder_test/Adder_test.runs/synth_1/vivado.jou
#-----------------------------------------------------------
source array.tcl -notrace
Command: synth_design -top array -part xc7vx485tffg1157-1 -flatten_hierarchy none
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx485t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 47597
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1401.051 ; gain = 86.996 ; free physical = 37601 ; free virtual = 85266
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'array' [/home/fpgauser5/Adder_test/Adder_test.srcs/sources_1/new/array.v:23]
WARNING: [Synth 8-3848] Net finished in module/entity array does not have driver. [/home/fpgauser5/Adder_test/Adder_test.srcs/sources_1/new/array.v:30]
INFO: [Synth 8-6155] done synthesizing module 'array' (1#1) [/home/fpgauser5/Adder_test/Adder_test.srcs/sources_1/new/array.v:23]
WARNING: [Synth 8-3331] design array has unconnected port finished
WARNING: [Synth 8-3331] design array has unconnected port reset
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 1445.684 ; gain = 131.629 ; free physical = 37615 ; free virtual = 85281
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 1445.684 ; gain = 131.629 ; free physical = 37616 ; free virtual = 85282
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1445.684 ; gain = 131.629 ; free physical = 37616 ; free virtual = 85282
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7vx485tffg1157-1

----------------------------------------------------------------------------------------------------------------------------------------------

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Moderator
Moderator
438 Views
Registered: ‎05-31-2017

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi @piyushmanavar ,

As you have modified the design (UUT) code, have you modified the testbench too so that instantiation of the ports matches with the UUT ?

If not please modify and share the error if you face any again while running post-synthesis simulation.

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380 Views
Registered: ‎01-30-2019

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Yes,

I have modified the testbench accordingly.. But got the same result.

are array can be synthesised in vivado? if I use it in port defination?

 

Thanks

-Piyush

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Moderator
Moderator
356 Views
Registered: ‎03-16-2017

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi @piyushmanavar ,

>>are array can be synthesised in vivado? if I use it in port defination?

You need to use System Verilog file type instead of verilog . Just change your RTL source file type to SV. 

 

And after that post your test bench if you still see face the same issue. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Moderator
Moderator
341 Views
Registered: ‎05-31-2017

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi @piyushmanavar ,

I did give a try on the modified code and I don't see any errors while running Post- Synthesis Functional Simulation.

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311 Views
Registered: ‎01-30-2019

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi,

I am still getting same error. I am using vivado 2018.2.

I tried the code with verilog and system verilog. In verilog, even functional simulation not working. After setting the the option  to system verilog, functional stimulation is working but after synthesis functional simulation is not working..

Can you please let me know your configuration? Version and other settings , If possible?

Thanks..

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305 Views
Registered: ‎01-30-2019

Re: Post synthesis simulation not working, But Behavioral Simulation is working

Hi,

You have said that you done some modification in code. Did you modify the port defination to get it synthesized?

 

Thanks..

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