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Gabriel_94
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Newbie
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Registered: ‎07-31-2020

Post synthesis simulation problem

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Hi, I'm Gabriel.

I'm trying to build a buffer to store matrix, which can write column data and read row/column data, respectively.

So I've designed the architecture with column-wise pipe registers with two data outputs for row and column data.

Row data is read by concatenated bits from column data.

The problem happens after synthesis that behavioral simulation shows proper functioning; however, post-synthesis timing/functional simulation shows that

the column input data doesn't store properly.

Outputs from buffer also wrong as the input isn't stored for the few first and few last addresses.

 

So, I judged that the synthesis might have removed some wires and registers, and that could have yielded such simulation results.

I've tried "(*keep = "true"*)" options, which didn't work.

I have no idea what could be done.

Please, help, and thank you in advance.

 

I'm attaching Verilog codes and the result of simulations to help to understand.

 

Thank you

 

 

Behavioral_simulation.jpg
Post_synth_simulation.jpg
Architecture.jpg
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calibra
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Scholar
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Registered: ‎06-20-2012

@Gabriel_94 

It is a bug.

The design synthesized with Mentor Graphics Precision simulate well.

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pulim
Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

Hi  @Gabriel_94 

Can you share PipeReg module also to reproduce this issue at my end?

In which version of vivado are you seeing this issue?

Can you try using DONT_TOUCH attribute and see if that helps?

 

Thanks,

Manusha

 

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Gabriel_94
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Registered: ‎07-31-2020
module PipeReg #(parameter  BITWIDTH = 1) (
    input   wire                        CLK,
    input   wire                        RST,
    input   wire                        EN,
    input   wire    [BITWIDTH-1 : 0]    D,
    output  reg     [BITWIDTH-1 : 0]    Q
);

    always @ (posedge CLK)
    begin 
        if (RST)        Q <= {BITWIDTH{1'b0}}; 
        else if (EN)    Q <= D;
    end
 
---------------------------------------------------------------
Thank you for your reply.
 
-the version of the vivado
I'm using 2019.1 version of vivado at the moment.
 
Thank you for your advise, I will check if DONT_TOUCH attribute works and let you know!
 
Thanks again,
Gabriel
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Gabriel_94
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Registered: ‎07-31-2020
I have tried (* dont_touch = "true" *), it didn't work on post-synthesis simulation.
Thank you for your advice!
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calibra
Scholar
Scholar
831 Views
Registered: ‎06-20-2012

@Gabriel_94 

It is a bug.

The design synthesized with Mentor Graphics Precision simulate well.

== If this was helpful, please feel free to give Kudos, and close if it answers your question ==

View solution in original post

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Gabriel_94
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Newbie
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Registered: ‎07-31-2020
Thank you, I have checked on another simulation tool and worked fine.
Have a good day
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