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Participant
Participant
6,100 Views
Registered: ‎07-11-2009

Problem during syntheis: Found Circular Dependency

Hi!

    I got some sysgen generated hdl netlists. These netlists has been instiantiated in a top level VHDL module in xilinx ISE. These modules are interconnected with each other to form a closed loop (system with feedback). I was able to sucessfully synthesize this design and test in FPGA board. Later on, I made some changes in it and tried to synthesize it again. The change that I made was just to add one more flip flop to increase delay. But this time, I could not synthesize it. I got the following warnings and errors,

 

WARNING:ProjectMgmt:454 - File circular dependency detected using rule: define-before-use.
WARNING:ProjectMgmt:455 - Found circular dependency consisting of the following files:
WARNING:ProjectMgmt -           C:/drivef/cur_reference/cur_reference.vhd
WARNING:ProjectMgmt -           C:/drivef/control_m/control_m.vhd
WARNING:ProjectMgmt -
WARNING:ProjectMgmt:455 - Found circular dependency consisting of the following files:
WARNING:ProjectMgmt -           C:/drivef/cur_reference/cur_reference.vhd
WARNING:ProjectMgmt -           C:/drivef/control_m/control_m.vhd
WARNING:ProjectMgmt -

WARNING:ProjectMgmt -
WARNING:ProjectMgmt:423 - Breaking file dependency loop(s) to create a compile order.
WARNING:ProjectMgmt:445 - Due to the above cyclic loop(s) a valid compile order could not be generated.
Reading design: driver_top.prj
ERROR:Xst:2369 - Empty project file "C:\drivef\driver_top\driver_top.prj"

 

Is there any way to solve this issue?

 

Milan

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Visitor
Visitor
5,933 Views
Registered: ‎03-15-2010

I have the exact same problem.  I also have a project that includes two lower-level SysGen-generated sources connected together at the top-level schematic.  I have compiled this design many times over the last few months with no problem with just one SysGen-generated source but have recently added a second SysGen source and now I am having this problem.  The problem must be related to having multiple SysGen sources in a project.  Like the OP, my design successfully synthesized the first time but, after making some changes (at the top-level only), the design will not synthesize again.  I have run "Cleanup Project Files" and have re-generated the SysGen designs but still get this error.  Does anyone know the solution to this problem?  I may end up having to combine my two SysGen files - it was just more convenient to split the SysGen part of the design up into more manageable, functionally-separate entities.  Thanks.
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Participant
Participant
5,927 Views
Registered: ‎07-11-2009

Hi Distanley,

                     I tried my best to get it to work  with 10.1. My advice is instead of making separate sysgen files for each functional blocks and instantiating in xilinx ISE top level module, just put everything in a single sysgen file if that's possible and instantiate in xilinx ISE. It works well without any problem (at least for me).

 

 

Milan

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Visitor
Visitor
5,920 Views
Registered: ‎03-15-2010

Hi.  I suspected I would need to combine both SysGen sources into one because I've compiled many times before with just one SysGen source without any problems but the first time I added a second SysGen-generated vhdl file, I started having problems.  I have opened a web case with Xilinx.  I'll post if they are able to find a solution that allows multiple SysGen sources in the same ISE project.  Thanks for the reply.
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Newbie
Newbie
4,118 Views
Registered: ‎12-17-2013

The solution is to put each Sysgen module in a separate library.  Sysgen seems to also include a common package in all of its outputs, so when you use more than one in the same library you get conflicts.  (In  Modelsim, it shows up as having to recompile because a package changed.  Then, when you recompile, you get the error message for the other module.)

 

However, if you manage things by putting each Sysgen product in its own libary, these problems (simulation & synthesis) go away.

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