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yassino
Visitor
Visitor
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Registered: ‎08-24-2017

Problem in switching an inout port between a reading and a writing mode

Hi,

I designed a component to switch between two modes : read(sending data out of the FPGA) and write(receiving data from an external board), this is the VHDL code of the component :

-----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity inet is
    Port ( GLCD_DATA_WRITE : in    STD_LOGIC;
           GLCD_DATA_READ  : out   STD_LOGIC;
           CONTROL         : in    STD_LOGIC;
           GLCD_PINS       : inout STD_LOGIC);
end inet;

architecture Behavioral of inet is

begin

PROCESS(CONTROL,GLCD_DATA_WRITE)
BEGIN
   IF(CONTROL = '0') THEN -- WRITE
      GLCD_PINS <= GLCD_DATA_WRITE;
   ELSE
      GLCD_PINS <= 'Z'; -- SET AS HIGH IMPEDANCE INPUT
   END IF;
END PROCESS;


GLCD_DATA_READ <= GLCD_PINS;

end Behavioral;

-----------------------------------------------------------------------------------

 

Unfortunately, I'm remarking that this component works only if I want to send a data out of my FPGA (when the Control signal is set to 0) and I verified this with my logic analyzer. But, when I want to read a data which is entered in the same inout pin(when the Control signal is set to 1), It dosen't work!
Please can you help me if I missed something in my design or I choosed the wrong component for my application.

Thank you in advance.

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13 Replies
hpoetzl
Voyager
Voyager
4,977 Views
Registered: ‎06-24-2013

Hey @yassino,

 

Seems to work here as expected, here the version I checked with Vivado 2017.2:

entity top is
    port (
        control : in std_logic;
        write : in std_logic;
        read : out std_logic;
        pin : inout std_logic
    );
end entity;

architecture RTL of top is
begin
    process (control, write)
    begin
        if control = '0' then
            pin <= write;
        else
            pin <= 'Z';
        end if;
    end process;

    read <= pin;
end RTL;

Which results in the following schematic (which is what you describe):

schematic.png

Note that personally I'd code it a little more compact like this:

    pin <= write when control = '0' else 'Z';
    read <= pin;

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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yassino
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Registered: ‎08-24-2017

Hi,

Thank you for your answer.

Yes my design is the same as your, and I got the same post-synthesis schematic but it doesn't work.

Note: I'm working with Vivado 2016.4.
RK : the I/O ports of the components are directly connected to the GPIO pins of the FPGA through IO ports,
so I would like to know if I have to set some particular parameters to my GPIO pins like IO std, Pull type… ?
I'm just trying to understand the problem because if the component is properly designed and one of its mode(sending) is working well so why it doesn't switch the line to receive data.

Thank you for your help.

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hpoetzl
Voyager
Voyager
4,968 Views
Registered: ‎06-24-2013

Hey @yassino,

 

Thank you for your answer.

You're welcome!

 

I got the same post-synthesis schematic but it doesn't work.

Well, looking at the implementation result, everything looks as expected as well:

iobuf.png

I've marked the control input in red, the write input in blue, the read output in green and the pin connection in white.

 

I would like to know if I have to set some particular parameters to my GPIO pins like IO std, Pull type… ?

You should definitely set the IO Standard, otherwise the pin might not work as expected.

 

For me the main question is, how do you test this and what exactly fails for you?

 

Best,

Herbert

-------------- Yes, I do this for fun!
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yassino
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Registered: ‎08-24-2017

You should definitely set the IO Standard, otherwise the pin might not work as expected.

Yes off course I putted it OI standard and this was not the reason.

For me the main question is, how do you test this and what exactly fails for you?

So, my design consists of sending first some bits from my FPGA to the external target when the Control signal is set to 0 and then after finishing the sending of the data, the Control signal is switched to 1 and here I have to receive a response from the target.
the first part is working well and I verified it using the logic analyzer but the reception mode is not working, I eliminated the probability that the target is not well configured by tried to  to enter a '1' Logic into my FPGA's GPIO pin (by just powering it with Vcc) but it doesn't work also(nothing is entering in the inout line).

Best,

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yassino
Visitor
Visitor
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Registered: ‎08-24-2017

It seems like the inout port is default to the Output mode !!
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hpoetzl
Voyager
Voyager
4,952 Views
Registered: ‎06-24-2013

Hey @yassino,

 

It seems like the inout port is default to the Output mode !!

Not sure what you are trying to say here ... please elaborate!

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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yassino
Visitor
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Registered: ‎08-24-2017

I want to say that an inout port which you add to your design in order to connect the ports of the components to the GPIO's of your FPGA is set to output mode (the default state) and if I want to make it changing the data in both sides I have to do other configuration(I said It looks like this but I'm not sure about this).
You can find attached a figure of my component connected to the external pins of the FPGA in the bloc design.
In the pin named ''eins'' I'm watching the exchange of the data which happens in the inout pin named "innto".
Screenshot from 2017-08-24 19-55-54.png

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hpoetzl
Voyager
Voyager
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Registered: ‎06-24-2013

Hey @yassino,

 

In the pin named ''eins'' I'm watching the exchange of the data which happens in the inout pin named "innto".

Which will always reflect the value on the pin pad, regardless of the control selection (see device image above).

 

Best,

Herbert

-------------- Yes, I do this for fun!
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yassino
Visitor
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4,933 Views
Registered: ‎08-24-2017

Hi Hpoetzl,

Yes you're right. But this did not help me to solve the problem.
On the other hand, I'm finding an error in the synthesis :

 

[Designutils 20-1595] In entity inet, connectivity of net PINS cannot be represented in VHDL. VHDL lacks syntax to connect the following inout terminals to a differently-named net: inout PINS

Resolution: Check whether terminals really need inout direction and substitute input or output as needed. It may also be possible to rename the net to match the terminal.

 

But, I did not understand what I'm supposed to correct!
If this was the reason of my problem.

Best,

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hpoetzl
Voyager
Voyager
3,944 Views
Registered: ‎06-24-2013

Hey @yassino,

 

[Designutils 20-1595] In entity inet, connectivity of net ...

That is definitely a weird one to get in your simple setup, can you upload your project?

(Not sure how you tested your design with an error at the synthesis level though :)

 

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
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yassino
Visitor
Visitor
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Registered: ‎08-24-2017

Hey,

Yes this looks so weird but this is what I'm facing.
OK please find attached the project compressed.

Thank you for your help.

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hpoetzl
Voyager
Voyager
3,934 Views
Registered: ‎06-24-2013

Hey @yassino,

 

OK please find attached the project compressed.

This is only the project file not the entire project, so most files including the block design are missing.

 

Anyway, in the project file I saw that there is a system_ooc.xdc, which might be related to your problem.

When the code you are working with is an IP which gets compiled out of context, it might be that the ports are 'optimized away' and will later cause the error as well as a non functional design.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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yassino
Visitor
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Registered: ‎08-24-2017

Hey @hpoetzl,

''When the code you are working with is an IP which gets compiled out of context, it might be that the ports are 'optimized away' ''

I'm not sure if I understood you well.
Do you mean that I have to add the source code of the component in the general project and not develop it in other project and add it as an IP !
Is this problem related to the project Hierarchy (choosing the top level module for example) !?
Thank you for your help.

Best,

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