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Adventurer
Adventurer
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Registered: ‎12-04-2018

Problem synthesizing a mixed language project when adding a multidimensional array in Verilog using Vivado 2018.3

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Hello,

I am trying to connect the top level of my design to a core which its top level(Let's call it X) is in VHDL but the sub-modules of it are in verilog.

When I run the synthesis this error appears and it points at to first sub-module of X. [Synth 8-485] no port "A' on instance

The error is about an specific connection which is a two dimensional signal(A).

Here is part of the package that is used for signal A :

type vector32 is array (natural range <>) of std_logic_vector(31 downto 0);

and here is port declaration of top level X and the port A:

A  : out vector32(7 downto 0);

and here is the first sub module of A and the port declaration of it which is in Verilog:

output wire 	  [7:0] [31:0]  A,

 First, I tried the normal way of 2-dimensional port declaration in the Verilog so I had the following:

output wire [31:0] A [7:0] 

but I was receiving a syntax error that "port A must not be declared to be an array. and in the connection between this module and the one under it in hierarchy, I was getting this error : Cannot access memory 'A' directly. so I changed it to be output wire [7:0] [31:0] A.

Can somebody help me with that ?

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Scholar
Scholar
480 Views
Registered: ‎09-16-2009

There's no industry standard to define the boundary between verilog and VHDL.  As multi-dimensional arrays as first class citizens are a relatively new feature in Verilog (SystemVerilog around 2005 ish), one can see supporting this on inter-language boundaries may be dicey for tools.

I'd limit your interface between languages to simple 1-d bit vectors.  It's easy on the Verilog side to blast, and un-blast from single dimensional arrays to multi-dimensional arrays if you use packed vectors; usually a simple assignment is all that is required.  I can't comment on how to do this on the VHDL side of things.

It's always been common to require a "wrapper" level of hierarchy when crossing language boundaries in a mixed language design - for many reasons.  I'd stick this sort of thing in that wrapper level.

Regards,

Mark

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2 Replies
Scholar
Scholar
481 Views
Registered: ‎09-16-2009

There's no industry standard to define the boundary between verilog and VHDL.  As multi-dimensional arrays as first class citizens are a relatively new feature in Verilog (SystemVerilog around 2005 ish), one can see supporting this on inter-language boundaries may be dicey for tools.

I'd limit your interface between languages to simple 1-d bit vectors.  It's easy on the Verilog side to blast, and un-blast from single dimensional arrays to multi-dimensional arrays if you use packed vectors; usually a simple assignment is all that is required.  I can't comment on how to do this on the VHDL side of things.

It's always been common to require a "wrapper" level of hierarchy when crossing language boundaries in a mixed language design - for many reasons.  I'd stick this sort of thing in that wrapper level.

Regards,

Mark

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471 Views
Registered: ‎01-22-2015

@m.yaghmai 

As markcurry says, the allowed types for ports is limited when you are mixing VHDL and Verilog in Vivado.  For details see Chapter 9 in UG901(v2020.1).  Specifically, see "Port Mapping" on pages 291-292 of UG901.

Mark