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Adventurer
Adventurer
9,719 Views
Registered: ‎08-24-2008

Problem when using IEEE.std_logic_textio Package

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Hello Every one..

 

Im working on a project and need to write some signal vectors of type STD_LOGIC_VECTOR  into a TEXT file on my hard drive to use it in MATLAB.

So Im trying to use the IEEE.STD_LOGIC_TEXTIO package to write these signals and i start to learning the using of this package with this very simple counter code

 


1library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.std_logic_textio.all;
use std.textio.all;

entity counter is
    Port ( clk : in  STD_LOGIC;
              output : out  STD_LOGIC_VECTOR (7 downto 0));
end counter;

architecture Behavioral of counter is
signal temp : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal stop : STD_LOGIC_VECTOR (7 downto 0):="10000000";

begin
process(clk,temp)
      file f : TEXT open WRITE_MODE is "f.txt";
        variable L : LINE;
begin
   if clk'event and clk='1' then
      if temp <= stop then
            temp <= temp + "00000001";
                write(L, temp);   -- line 26
              writeline(f,L);
      end if;
   end if;
end process;
output <= temp;
end Behavioral;

 

But when I synthesize this code the following error apear:

 

Analyzing Entity <counter> in library <work> (Architecture <behavioral>).
ERROR:Xst:2215 - "D:/Xilinx92i/work/test/test.vhd" line 26: Second argument of write must have a constant value.
-->

 

What is the mistake in the code , PLEASE guide me to correct any error in my code . I need your HELP

for Knowlege, im using ISE 9.2i and Spartan 3E FPGA.

 

Thanks

oms
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1 Solution

Accepted Solutions
Mentor hgleamon1
Mentor
12,992 Views
Registered: ‎11-14-2011

Re: Problem when using IEEE.std_logic_textio Package

Jump to solution

Why are you trying to synthesise this?

 

You are mixing functional and behavioural VHDL. You can't synthesise something that is trying to WRITE A TEXT FILE in this way.

 

What happens when you simulate this, instead?

 

Regards,

 

Howard

 

 

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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6 Replies
Mentor hgleamon1
Mentor
12,993 Views
Registered: ‎11-14-2011

Re: Problem when using IEEE.std_logic_textio Package

Jump to solution

Why are you trying to synthesise this?

 

You are mixing functional and behavioural VHDL. You can't synthesise something that is trying to WRITE A TEXT FILE in this way.

 

What happens when you simulate this, instead?

 

Regards,

 

Howard

 

 

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Adventurer
Adventurer
9,712 Views
Registered: ‎08-24-2008

Re: Problem when using IEEE.std_logic_textio Package

Jump to solution

Dear hgleamon1

 

I Thank You very much for this quick reply.

I simulate the code and it works properly, I found the text file contains the correct data.

 

Thanks alot..

 

oms
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Historian
Historian
9,701 Views
Registered: ‎02-25-2008

Re: Problem when using IEEE.std_logic_textio Package

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@mr_computer wrote:

Dear hgleamon1

 

I Thank You very much for this quick reply.

I simulate the code and it works properly, I found the text file contains the correct data.

 

Thanks alot..

 


You're completely confusing synthesis and simulation.

----------------------------Yes, I do this for a living.
Highlighted
Newbie ele4add
Newbie
9,294 Views
Registered: ‎08-26-2013

Re: Problem when using IEEE.std_logic_textio Package

Jump to solution

Dear mr_computer,

 

Now i have the same problem as you. Im working on a project and need to write some signal vectors of type STD_LOGIC  into a TEXT file on my hard drive to use it in MATLAB.

 

Can you give me some materials?

My Email Address is: sxylsmxuping@163.com

 

Thanks very much.

Tags (1)
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Newbie nancyfancy
Newbie
8,523 Views
Registered: ‎05-14-2014

Re: Problem when using IEEE.std_logic_textio Package

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Thank you both of you. I have been searching for this solution for a while and found solution. Thanks a lot !!
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Newbie karion
Newbie
6,546 Views
Registered: ‎03-14-2015

Re: Problem when using IEEE.std_logic_textio Package

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where did you find this solution?

 

thanks

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