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Visitor yribot
Registered: ‎03-06-2019

Problem with LUT Combining (ISE)

I did a proyect (in Verilog) for a Virtex-7 platform in Vivado version 2018.3. This design consumes 128 5-LUT. Due to each couple of 5-LUT have the same 5 inputs and I used the synthesis strategy: "Flow Area Optimized High", now the desing consumes 64 6-LUT.
Now I am working with a Virtex-6 (XC6VLX75 FF784) plataform in ISE (for Windows 7) version 14.7. I am using the same code and I have select the design strategy: "Area Reduction", and select LUT Combining: "Area", but the device utilization summary shows that the desing consumes 128 5-LUT. Why does this happen? Why does not it show 64 6-LUT?
Thank in advance

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2 Replies
Scholar dpaul24
Registered: ‎08-07-2014

Re: Problem with LUT Combining (ISE)


I am not surprised by the results. Because one is ISE and the other is Vivado.

The internal algos of Vivado are much improved than ISE. Probably this is the reason.

FPGA enthusiast!
All PMs will be ignored
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Mentor jmcclusk
Registered: ‎02-24-2014

Re: Problem with LUT Combining (ISE)

The usual solution when the synthesis tool fails to create a LUT_6_2 element, is to instantiate this primitive in your code.   This usually locks it down nicely, and if the tools give you any trouble, you can nail the gates down by using a DONT_TOUCH attribute.    This gives the tools zero latitude to mess things up.

Don't forget to close a thread when possible by accepting a post as a solution.
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