Problem with Verilog system task $ceil

[david.hoffman]

I'm having trouble using the $ceil system task.

I have the following parameters that define the number of bits used for a counter:

parameter BITS_PER_WORD = 32

localparam real BYTES_PER_WORD = BITS_PER_WORD / 8;
localparam real BYTES_PER_PACKET = 190;
localparam integer WORDS_PER_PACKET = $ceil(BYTES_PER_PACKET / BYTES_PER_WORD); 
localparam WORD_CNTR_BITS = $clog2(WORDS_PER_PACKET);

These parameters resolve to the following values (from the Vivado synthesis log): 

 Parameter BITS_PER_WORD bound to: 32 - type: integer 
 Parameter BYTES_PER_WORD bound to: 4.000000 - type: float 
 Parameter BYTES_PER_PACKET bound to: 190.000000 - type: float 
 Parameter WORDS_PER_PACKET bound to: 0.000000 - type: float 
 Parameter WORD_CNTR_BITS bound to: 0 - type: integer 

I expect WORDS_PER_PACKET to be ceil(190.0 / 4.0) = ceil(47.5) = 48.0

And therefore expect WORDS_CNTR_BITS to be 6.

Furthermore, I would expect the type of BYTES_PER_PACKET to of type integer since it is explicitly declared as an integer but the tool is reporting it as a float.

Am I using $ceil incorrectly here?

Thanks,

David

[david.hoffman · Accepted solution]

My original post was using Vivado 2018.2. When I upgraded to Vivado 2018.3 and compiled the same code the issue was resolved:

	Parameter WIDTH bound to: 32 - type: integer 
	Parameter BYTES_PER_WORD bound to: 4.000000 - type: float 
	Parameter BYTES_PER_PACKET bound to: 190.000000 - type: float 
	Parameter WORDS_PER_PACKET bound to: 48 - type: integer 
	Parameter WORD_CNTR_BITS bound to: 6 - type: integer 

I would have thought something like this would be caught in Xilinx's regression testing before release!