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arash9k
Adventurer
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Registered: ‎02-12-2013

Problem with $readmemh at synthesis in Vivado

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Hi,

 

I'm using Vivado 2013.2 and I'm having problems with $readmemh. I have three modules: A, B, and C. Module A is the top module. It calls module B, and module B calls module C. I pass the name of a file from A to B, then from B to C. Module C in turn runs the command: $readmemh (filename , table , start , end).

 

The filename is in the form "../../../myfilename.txt". I did this because I have the file in the project's main directory, but my source files are three levels into the main directory.

 

Everything works fine (ie I can read the file) when simulating, however during synthesis I get this warning message:

 

[Synth 8-2898] ignoring malformed $readmem task: invalid memory name

 

Everything else in my program doesn't work as a result of this, because the synthesis process basically ignores my file.

 

However, when I use readmemh inside module A (ie the top module) and synthesize, I don't see the warning and everything is OK. All modules (A, B, and C) are in the same directory.

 

Can anybody help me with this? Why is synthesis complaining when I use readmemh from module C?

 

Thanks,

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arash9k
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Registered: ‎02-12-2013

$readmemh doesn't work when you access it's second argument by a constant (or an integer) later on in the design. So if you have $readmemh(filename, table, start, end) and later on you use table[i] to get the ith row, where i is an integer or genvar, $readmemh will not be able to read the file. If you want to access "table" row by row you have to use a wire or a reg as the index.

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arash9k
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Registered: ‎02-12-2013

$readmemh doesn't work when you access it's second argument by a constant (or an integer) later on in the design. So if you have $readmemh(filename, table, start, end) and later on you use table[i] to get the ith row, where i is an integer or genvar, $readmemh will not be able to read the file. If you want to access "table" row by row you have to use a wire or a reg as the index.

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paulrobert
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Registered: ‎05-04-2014

Hi guys, I had the same problem but in my Verilog is declared as:

 

// Memory Array
reg [31:0] memory[0:1023];

initial
begin
$readmemh("../Software/code.hex", memory);
end

 

WARNING: [Synth 8-2898] ignoring malformed $readmem task: invalid memory name

 

How to fix that?

 

Thanks

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hj
Moderator
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13,373 Views
Registered: ‎06-05-2013
Check page 226 for proper coding example.
http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf

I hope this may help you.

Regards,
Harry
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paulrobert
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Registered: ‎05-04-2014

The command is like the example of page 226. But in the example, he uses readmemb, but the structure should be the same for readmemh, right?

 

Another question is, when I compile using Vivado, where should I put this file? Into the same folder of verilog or in the folder where the project is run?

 

Do Memory and mem are reserved words?

 

Thanks.

 

Best Regards,

 

Paulo

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paulrobert
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Registered: ‎05-04-2014

Hi,

 

The problem still present.

 

But one thing that I tested is putting the task on top level A. If task is present on Verilog top level, its work, but if I use in a sub block B instantiate on A, occurs this error. Why?

 

Thanks for the support.

 

 

Best regards.

 

Paulo

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geniooo
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Registered: ‎03-21-2015

hi,

please can help me , 

i have same problem 

thanks 

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