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szewcu12
Newbie
Newbie
517 Views
Registered: ‎03-17-2021

Problem with warnings "Latches may be generated..."

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Hi,

I have problems with my code:

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity LCD is port (
clk: in std_logic;
stan: in std_logic;
E_LCD: out std_logic;
DC_LCD: out std_logic;
D_LCD: out std_logic_vector(7 downto 0)
);
end LCD;

architecture Behavioral of LCD is

type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
attribute enum_encoding: string;
attribute enum_encoding of state_type: type is "0001 0010 0011 0100 0101 0110 0111 1000 1001";

signal cs: state_type :=s0;
signal ns: state_type;
signal CLK_400Hz: STD_LOGIC;
signal CLK_400cnt: integer range 0 to 1300000;
begin

u1: process(clk)
	begin
	if(clk' event and clk='1') then
	CLK_400cnt <= CLK_400cnt+1;
	if (CLK_400cnt=10000) then
		cs <= ns;
		CLK_400Hz <= not CLK_400Hz;
		CLK_400cnt <= 0;
	end if;
	end if;
	end process;

u2: process(cs)
	begin
		case cs is
		when s0 =>
			ns<=s1;
			DC_LCD <= '0'; --lcd control
			D_LCD <= x"01"; -- lcd init
		when s1 =>
			DC_LCD <= '0';
			D_LCD <= x"0c";
			ns<=s2;
		when s2 =>
			DC_LCD <= '0';
			D_LCD <= x"06";
			ns<=s3;	
		when s3 =>
			DC_LCD <= '0';
			D_LCD <= x"38";
			ns <= s4;
		when s4 =>
			DC_LCD <= '0';
			D_LCD <= x"C0";
			ns <= s5;
		when s5 =>
			DC_LCD <= '0';
			D_LCD <= x"02";
			ns <= s6;
		when s6 =>
			DC_LCD <= '0';
			D_LCD <= x"01";
			ns <= s7;
		when s7 =>
			if (stan = '0') then
			ns <= s8;
			else
			ns <= s5;
			end if;
		when s8 =>
			DC_LCD <= '1';
			D_LCD <= x"42";
			ns <= s5;	
		when others =>
			ns <= s0;
			DC_LCD <= '0';
			D_LCD <= x"00";
			end case;
	
	end process;
	
E_LCD <= CLK_400Hz;
end Behavioral;

Here is warnings:

Found 8-bit latch for signal <D_LCD>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <DC_LCD>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

I can't find this latches. For first look on code, everything looks good. Maybe someone can find solution.

THANKS!

0 Kudos
1 Solution

Accepted Solutions
drjohnsmith
Teacher
Teacher
475 Views
Registered: ‎07-09-2009

Well

 

Where are you learning VHDL ?

I strongly suggest a good book, as what your showing has a few bad deign bits.

suggest .

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

So to your code,

as stated above,

   Latches are formed when the code does not say where the output should go next.

 

Using  a two process state machie, especialy a long one , is almost garunteed to make a mistake.

    Use the single process style.

 

Second, why did this not show up in simulation ?

    You should always simulate before synthesising,

         Get used to it , you will spend 90 percent of your life in simulation, so learn it now it will save you in the future making big mistakes.

 

Libraries.

i assume thats a cut paste problem in the first line , but

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

Do not  ever use sts_logic_arith

do a google search, but 

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html

 

next , do not use 

if(clk' event and clk='1') then

 

use if rising-edge ( clk ) then

 

have fun 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

3 Replies
richardhead
Scholar
Scholar
508 Views
Registered: ‎08-01-2012

Latches are generated when a signal is not assigned a value in all cases of an asynchronous proocess. In your 2nd process, u2, DC_LCD and D_LCD are not assigned a value when cs = s7. To avoid this, ensure they are assinged a value in this state, or make sure they are given a default value at the start of the process.

I also note you are missing "stan" signal from the sensitivity list. Hence simulation will not match actual hardware (synthesis ignores sensitivity lists).

To avoid latches, as a beginner, the single process state machine style is often recommended.

 

dpaul24
Scholar
Scholar
500 Views
Registered: ‎08-07-2014

@szewcu12 ,

Strongly recommended - "To avoid latches, as a beginner, the single process state machine style is often recommended."

Please change your coding style.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

drjohnsmith
Teacher
Teacher
476 Views
Registered: ‎07-09-2009

Well

 

Where are you learning VHDL ?

I strongly suggest a good book, as what your showing has a few bad deign bits.

suggest .

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

So to your code,

as stated above,

   Latches are formed when the code does not say where the output should go next.

 

Using  a two process state machie, especialy a long one , is almost garunteed to make a mistake.

    Use the single process style.

 

Second, why did this not show up in simulation ?

    You should always simulate before synthesising,

         Get used to it , you will spend 90 percent of your life in simulation, so learn it now it will save you in the future making big mistakes.

 

Libraries.

i assume thats a cut paste problem in the first line , but

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

Do not  ever use sts_logic_arith

do a google search, but 

https://www.nandland.com/articles/std_logic_arith_vs_numeric_std.html

 

next , do not use 

if(clk' event and clk='1') then

 

use if rising-edge ( clk ) then

 

have fun 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post