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Anonymous
Not applicable
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Problems getting going with ISE

i'm getting around to working with ise webpack 11.3 and i'm stumped with a model that uses vital

 

     
LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;
    USE IEEE.VITAL_timing.ALL;
    USE IEEE.VITAL_primitives.ALL;

 

It can't find the VITAL package, (Library unit VITAL_primitives is not available in library IEEE.) i've searched all over and i can see some VDB files, but not much else, i did see some posts on VITAL2000 vs VITAL, but that din't work either. I'm missing something obvious, but i've been googling for about an hour now.,

 

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Anonymous
Not applicable
9,349 Views

welll i got Vital going, but not i've got a "Line 367. Port unsupported in block concurrent statement." mesage...

 

 

   Behavior: BLOCK

        PORT (
            A              : IN    std_logic_vector(HiAddrBit downto 0) :=
                                               (OTHERS => 'U');
            DIn            : IN    std_logic_vector(15 downto 0) :=
                                               (OTHERS => 'U');
            DOut           : OUT   std_ulogic_vector(15 downto 0) :=
                                               (OTHERS => 'Z');
            CENeg          : IN    std_ulogic := 'U';
            OENeg          : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            RESETNeg       : IN    std_ulogic := 'U';
            BYTENeg        : IN    std_ulogic := 'U';
            RY             : OUT   std_ulogic := 'U'
        );
        PORT MAP (

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paloma
Newbie
Newbie
9,201 Views
Registered: ‎11-17-2009

Hi!

I'm having the same problem with a vhdl model I want to use. I'm getting the same error: "Library unit VITAL_primitives is not available in library IEEE"

In the other post you say you managed to get it working...How did you solve it?

By the way, I'm using WebPack 11.1

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bassman59
Historian
Historian
9,197 Views
Registered: ‎02-25-2008


charliex wrote:

welll i got Vital going, but not i've got a "Line 367. Port unsupported in block concurrent statement." mesage...

 

 

   Behavior: BLOCK

        PORT (
            A              : IN    std_logic_vector(HiAddrBit downto 0) :=
                                               (OTHERS => 'U');
            DIn            : IN    std_logic_vector(15 downto 0) :=
                                               (OTHERS => 'U');
            DOut           : OUT   std_ulogic_vector(15 downto 0) :=
                                               (OTHERS => 'Z');
            CENeg          : IN    std_ulogic := 'U';
            OENeg          : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            RESETNeg       : IN    std_ulogic := 'U';
            BYTENeg        : IN    std_ulogic := 'U';
            RY             : OUT   std_ulogic := 'U'
        );
        PORT MAP (


Simply put -- the code above is not legal VHDL. Blocks don't have ports. Please buy a copy of the Ashenden VHDL book.

 

What you probably want is a component declaration (which goes in the architecture BEFORE the "begin") and a component instance (the thing with the port maps) which goes in the main body of the architecture (after the begin).

 

----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
9,194 Views

I did buy a couple of books, so i'm working through them, but that is the code from the FMF, which has a lot of the same code reuse, so it must have worked somewhere , someplace!

 

for the vital 2000 i just used source from another tool that installed vital.

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bassman59
Historian
Historian
9,181 Views
Registered: ‎02-25-2008


charliex wrote:

I did buy a couple of books, so i'm working through them, but that is the code from the FMF, which has a lot of the same code reuse, so it must have worked somewhere , someplace!

 

for the vital 2000 i just used source from another tool that installed vital.


I stand corrected -- Section E.5 in Ashenden, Concurrent Statements, indicates that blocks may indeed have ports, port maps, generics and generic maps. I've never had a reason to use this construct; I've used named blocks but never any with ports/port maps.

 

However, you've never mentioned exactly which tool you are using, and it is likely that this construct is not supported.

----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
9,175 Views

Unless i need to be more specific about which tool, (in which case i'm not sure what info i need to provide)  i'm using then its ISE webpack 11.3 as noted in the first post.

 

cheers.

 

 

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bassman59
Historian
Historian
9,166 Views
Registered: ‎02-25-2008


charliex wrote:

Unless i need to be more specific about which tool, (in which case i'm not sure what info i need to provide)  i'm using then its ISE webpack 11.3 as noted in the first post.

 

cheers.

 

 


I meant: are you simulating or synthesizing?

----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
9,163 Views

Its the synthesis step thats failing.

 

I think thats where i've been going wrong with it all, the concept of synthesis vs simulation

 

My eventual goal is just to create an AM29F800BB chip with a Spartan 3, I'd come across the FMF libray and naively thought i could just throw it in and get going, I did do a few other projects first, but i did skip some of the basics.  I'm still reading up though, so i've got some more studying to do before i come back to this stage. 

 

thanks for your help though.

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bassman59
Historian
Historian
9,161 Views
Registered: ‎02-25-2008


charliex wrote:

Its the synthesis step thats failing.

 

I think thats where i've been going wrong with it all, the concept of synthesis vs simulation


thanks for your help though.


oh, that's your problem.

 

The FMF models (and any VITAL models) are for simulation only.

----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
4,634 Views

ah thanks, i did have a sneaking suspicion thats why i was having issues, it just seems such an odd  error message, the FMF does list some of the models as sim only, the ise 11.3 tool seems broken for error searches, and none of them show up.

 

Well i guess a good learning experience would be implementing a 29f800 for simulation then!

 

cheers!

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paloma
Newbie
Newbie
4,600 Views
Registered: ‎11-17-2009

Hi,

 

I still haven't solved my problem :o/

I've downloaded the vhdl component description for a 74_245 integrated circuit (an 8bit transceiver) from the www.eda.org library,  and i want to add it to my design as a symbol in my schematic. But i'm not able to create a symbol for this source. I've aded the fmf library, with the gen_utils.vhd package, but i sitll get the following error:

 

"ERROR:HDLParsers:3014 - "C:/std245.vhd" Line 26. Library unit VITAL_primitives is not available in library IEEE."

 

I also get:

 

"WARNING:HDLParsers:3481 - Library fmf has no units. Did not save reference file "C:/std74vhdl/hdllib.ref" for it."

 

I've managed to find the vital_primitives.vhd and vital_timing.vhd packages from another tool that uses them (ModelSim) and i've inserted them in C:/Xilinx/11.1/ISE/vhdl/src/ieee.  I thought that would solve the problem, but the error remains the same!

Am i putting them in the wrong place? Where is the default ieee library that ISE uses?

Do you know any place were i can download vhdl descriptions of standard 74_xx integrated circuit components, apart from eda.org?

 

cheers! 

 

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bassman59
Historian
Historian
4,583 Views
Registered: ‎02-25-2008


paloma wrote:

Hi,

 

I still haven't solved my problem :o/

I've downloaded the vhdl component description for a 74_245 integrated circuit (an 8bit transceiver) from the www.eda.org library,  and i want to add it to my design as a symbol in my schematic. But i'm not able to create a symbol for this source. I've aded the fmf library, with the gen_utils.vhd package, but i sitll get the following error:

 

"ERROR:HDLParsers:3014 - "C:/std245.vhd" Line 26. Library unit VITAL_primitives is not available in library IEEE."

 

I also get:

 

"WARNING:HDLParsers:3481 - Library fmf has no units. Did not save reference file "C:/std74vhdl/hdllib.ref" for it."

 

I've managed to find the vital_primitives.vhd and vital_timing.vhd packages from another tool that uses them (ModelSim) and i've inserted them in C:/Xilinx/11.1/ISE/vhdl/src/ieee.  I thought that would solve the problem, but the error remains the same!

Am i putting them in the wrong place? Where is the default ieee library that ISE uses?

Do you know any place were i can download vhdl descriptions of standard 74_xx integrated circuit components, apart from eda.org?

 

cheers! 

 


You've downloaded a simulation model. It doesn't work for synthesis.

 

Do NOT make the newbie mistake of trying to make old-skool 74-series TTL parts fit into an FPGA. That's a complete waste.

----------------------------Yes, I do this for a living.
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