cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
5,249 Views
Registered: ‎08-05-2009

Problems involving portmaps

I would like to ask for any advice or opinion regarding my code below. I can't determine how to update operands used in portmaps. I would greatly appreciate if anyone could find time to answer my question. Attached are the parts of my code. Thank You.

 

Note: The components I created are running perfectly. They produce correct outputs. I get an undefined value for my res output. I honestly think my logic is correct but i do not know if the portmaps i made get it. This is a VHDL module.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           en : in  STD_LOGIC;
           opA : in  STD_LOGIC_VECTOR (3 downto 0);
           opB : in  STD_LOGIC_VECTOR (3 downto 0);
           res : out  STD_LOGIC_VECTOR (7 downto 0);
           done : out  STD_LOGIC);
end multiplier;

architecture Behavioral of multiplier is
signal number1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
signal number2 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
signal tempA : STD_LOGIC_VECTOR(3 downto 0);
signal tempB: STD_LOGIC_VECTOR(3 downto 0);
signal tempC: STD_LOGIC_VECTOR(3 downto 0);


    COMPONENT clahead_addr
    PORT(
        clk : IN std_logic;
        operandA : IN std_logic_vector(3 downto 0);
        operandB : IN std_logic_vector(3 downto 0);
        carry_in : IN std_logic;         
        sum : OUT std_logic_vector(3 downto 0);
        carry_out : OUT std_logic
        );
    END COMPONENT;
   
    COMPONENT shifter
    PORT(
        clk : IN std_logic;
        rst : IN std_logic;
        op1 : IN std_logic_vector(3 downto 0);
        op2 : IN std_logic_vector(3 downto 0);
        din : IN std_logic;         
        out1 : OUT std_logic_vector(3 downto 0);
        out2 : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   
    --Inputs
    SIGNAL clk1 :  std_logic;
    SIGNAL rst1 :  std_logic;
    SIGNAL din :  std_logic;
    SIGNAL oper1 :  std_logic_vector(3 downto 0);
    SIGNAL oper2 :  std_logic_vector(3 downto 0);
    SIGNAL operand1 :  std_logic_vector(3 downto 0);
    SIGNAL operand2 :  std_logic_vector(3 downto 0);
    SIGNAL carry_in :  std_logic := '0';

    --Outputs
    SIGNAL out1 :  std_logic_vector(3 downto 0);
    SIGNAL out2 :  std_logic_vector(3 downto 0);
    SIGNAL sum1 :  std_logic_vector(3 downto 0);
    SIGNAL carry_out1 :  std_logic;

begin

    uut1: shifter PORT MAP(
        clk => clk1,
        rst => rst1,
        op1 => sum1,
        op2 => oper2,
        out1 => out1,
        out2 => out2,
        din => carry_out1
    );
   
    uut2: clahead_addr PORT MAP(
        clk => clk1,
        operandA => operand1,
        operandB => operand2,
        carry_in => carry_in,
        sum => sum1,
        carry_out => carry_out1
    );
   
    process (clk,rst,en)
    begin
        if rst = '1' then
            res <= "00000000";
            tempA <= "0000";
            tempB <= "0000";
            done <= '0';
        end if;
       
    end process;
    process (en,number1,tempB)
    begin
        if en = '1' then
            tempA <= opA;
            tempB <= opB;
            done <= carry_out1;
            tempC <= "0000";
        end if;
       
        case number1 is
            when "0001" =>
                    if tempB(0) = '0' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        number1 <= "0010";
                    end if;
                    if tempB(0) = '1' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        number1 <= "0010";
                    end if;
            when "0010" =>
                    if tempB(0) = '0' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        number1 <= "0100";
                    end if;
                    if tempB(0) = '1' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        number1 <= "0100";
                    end if;
            when "0100" =>
                    if tempB(0) = '0' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        number1 <= "1000";
                    end if;
                    if tempB(0) = '1' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        number1 <= "1000";
                    end if;
            when others =>
                    if tempB(0) = '0' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        res(7) <= tempC(3); res(6) <= tempC(2); res(5) <= tempC(1); res(4) <= tempC(0);
                        res(3) <= tempB(3); res(2) <= tempB(2); res(1) <= tempB(1); res(0) <= tempB(0);
                        number1 <= "0001";
                    end if;
                    if tempB(0) = '1' then
                        operand1 <= tempC;
                        operand2 <= tempA;
                        oper2 <= tempB;
                        tempC <= out1;
                        tempB <= out2;
                        res(7) <= tempC(3); res(6) <= tempC(2); res(5) <= tempC(1); res(4) <= tempC(0);
                        res(3) <= tempB(3); res(2) <= tempB(2); res(1) <= tempB(1); res(0) <= tempB(0);
                        number1 <= "0001";       
                    end if;
                end case;
    end process;
end Behavioral;

 

 

 

Message Edited by adrialex on 08-05-2009 07:15 AM
Message Edited by adrialex on 08-05-2009 07:15 AM
0 Kudos
5 Replies
Highlighted
Historian
Historian
5,238 Views
Registered: ‎02-25-2008

Re: Problems involving portmaps

You have assignments to the signal res is both that goofy reset process, and in the large process with the case statement.

 

The larger problem is that your code is a mess. Completely wrong sensitivity lists are just part of it.

 

Buy a good VHDL textbook. 

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Visitor
Visitor
5,228 Views
Registered: ‎08-05-2009

Re: Problems involving portmaps

It's a multiplier code. Could you specify what exactly is the problem in my code? I don't quite get what your pointing out. I just wanted to know how to properly handle portmaps. I know that processes run simultaneously. My rst signal only becomes 1 after 1 clk cycle and changes to 0 after. The en signal is used to determine if the multiplier would get the inputs and returns to 0 after one clock cycle. All inputs signals are taken care of at my testbench. Thank You. I hope i provided enough info to be able to determine the problem in my code.
Message Edited by adrialex on 08-05-2009 04:21 PM
0 Kudos
Highlighted
Historian
Historian
5,208 Views
Registered: ‎02-25-2008

Re: Problems involving portmaps


adrialex wrote:
It's a multiplier code. Could you specify what exactly is the problem in my code? I don't quite get what your pointing out. I just wanted to know how to properly handle portmaps. I know that processes run simultaneously. My rst signal only becomes 1 after 1 clk cycle and changes to 0 after. The en signal is used to determine if the multiplier would get the inputs and returns to 0 after one clock cycle. All inputs signals are taken care of at my testbench. Thank You. I hope i provided enough info to be able to determine the problem in my code.
Message Edited by adrialex on 08-05-2009 04:21 PM

OK, you asked for it.

 

a) You use the deprecated std_logic_arith/unsigned libraries. And you're not doing any math that requires them!

 

b)  You have a process:

 

    process (clk,rst,en)
    begin
        if rst = '1' then
            res <= "00000000";
            tempA <= "0000";
            tempB <= "0000";
            done <= '0';
        end if;     
    end process;

 

which is senstive to three signals, clk, rst and en. But neither clk nor rst are used in that process.

 

c) You have another process, which starts with:

 

process (en,number1,tempB)
begin
    if en = '1' then
        tempA <= opA;
        tempB <= opB;
        done <= carry_out1;
        tempC <= "0000";
    end if;
       
    case number1 is

     ... etc etc.

    end case;

end process;

 

This process is sensitive to only three signals, yet looking at the various assignments' right-hand sides shows that it should be sensitive to a lot more signals (like carry_out1, tempA, tempC, out1, and out2). But it is NOT sensitive at all to number1 (which never appears on any assignment's right-hand side).

 

d) I've already noted that the signal en is driven in both processes. So are the signals done, tempA and tempB. This results in a multiple-driver error message in synthesis, and lots of red Xs in simulation.

 

e) I assume that both the shifter and the clahead_addr entities are synchronous and as such the whole design is not a large combinatorial mess.

 

f) The problem is most certainly NOT with your port maps. It's with the rest of your code as noted here.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Teacher
Teacher
5,193 Views
Registered: ‎08-14-2007

Re: Problems involving portmaps

Hi Bassman,

about c)

What's with the case selector?

 So the process is indeed sensitive to signal number1.

 

 

But, such a detail may drown in the vast number of mistakes you found in adrialex's code.

Good work!

 

Regards

  eilert

 

0 Kudos
Highlighted
Historian
Historian
5,182 Views
Registered: ‎02-25-2008

Re: Problems involving portmaps


eilert wrote:

Hi Bassman,

about c)

What's with the case selector?

 So the process is indeed sensitive to signal number1.

 

 

But, such a detail may drown in the vast number of mistakes you found in adrialex's code.

Good work!

 

Regards

  eilert

 


Yes, his code is an unmitigated disaster.

 

----------------------------Yes, I do this for a living.
0 Kudos