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manoj_xilinx
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Registered: ‎11-22-2016

Process VHDL - Question

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Hello All,

I have a basic question about VHDL process. I understand that if I want my code to execute as 'C' Language that is line by line sequential execution, then I need to use process statement. 

 

Take the following code snippet for example,

 

        process (sys_clk_p)
           begin
               if rising_edge (sys_clk_p) then
                    a <= '1'; 
                    b <= '1';
                    c <= '1';

            end if;
      end process;

 

a,b,c are internal signals which are initially in high impedance, and sys_clk_p is a clock of 100 mhz.

 

During simulation. I expect a to go high first, followed by b and then c.

 

But in simulation, as soon as rising edge of sys_clk_p comes, a, b, and c all becomes high at the same time. I expected sequential behavior, but it looks like a concurrent assignment. I am confused.

 

Please see the attached simulation waveform.

 

 

Thanks,

Manoj

 

 

wave.PNG
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u4223374
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5,317 Views
Registered: ‎04-26-2015

There isn't really a neat way to describe true sequential line-by-line execution in VHDL (or in Verilog). The HDL code maps very closely to FPGA hardware, and the FPGA hardware isn't designed for sequential execution.

 

I'm not great at VHDL, so take the following with a grain of salt.

 

When people talk about processes in VHDL doing sequential execution, what they mean is that this code would behave how you'd expect in C:

 

 

a := '1'; 
b := a;
a := '0';
c := a;

 

Obviously in C, you'd expect that this results in a = 0, b = 1, c = 0. VHDL will do the same. However, in the FPGA it's not implemented as sequential assignments - the synthesis tool just figures out how it can generate the correct result with combinational connections (in this case, just by connecting 'a' and 'c' to 0, and 'b' to 1).

 

The other type of assignment in VHDL is a signal assignment:

a <= '1'; 
b <= a;
a <= '0';
c <= a;

This does not behave how you might expect from C, because all of these assignments happen simultaneously. As a result, when the assignment "b <= a" occurs, "a <= 1" has not happened yet. "b" will take whatever value "a" had before this block was run. "c" will be in the same situation. "a" is actually set to both 1 and 0, and the language specification says that the later assignment wins. As a result, the final values here will be:

 

a = 0

b = <whatever "a" was before this block ran>

c = <whatever "a" was before this block ran>

 

 

If you do want sequential execution in VHDL or Verilog, you need to investigate how to build a state machine.

 

 

Also be wary of relying too much on the simulator. The simulator tends to implement VHDL or Verilog as-specified, which includes useful features like arbitrary delays. Many of these features cannot be implemented in hardware, and the synthesis tool will either ignore them (which tends to result in a lot of head-scratching) or throw an error.

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simozz
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Registered: ‎05-14-2017

.

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florentw
Moderator
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3,186 Views
Registered: ‎11-09-2015

Hi @manoj_xilinx,

 

In VHDL, in processes we talk about sequencial logic because if you have variable in the project, the will be assigned sequentialy

 

ex:

 

process (clk)

variable a,b,c : integer;

if (rising_edge(clk)) then

  a := in;

  b := a + 3;

  b := 4;

  out <= b;

end if;

 

So out will have the value 4. Everything is done in one clock cycle.

 

Sequential just mean all instruction execute in the order in which they appear. This does not mean that you have one per clock cycle

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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u4223374
Advisor
Advisor
5,318 Views
Registered: ‎04-26-2015

There isn't really a neat way to describe true sequential line-by-line execution in VHDL (or in Verilog). The HDL code maps very closely to FPGA hardware, and the FPGA hardware isn't designed for sequential execution.

 

I'm not great at VHDL, so take the following with a grain of salt.

 

When people talk about processes in VHDL doing sequential execution, what they mean is that this code would behave how you'd expect in C:

 

 

a := '1'; 
b := a;
a := '0';
c := a;

 

Obviously in C, you'd expect that this results in a = 0, b = 1, c = 0. VHDL will do the same. However, in the FPGA it's not implemented as sequential assignments - the synthesis tool just figures out how it can generate the correct result with combinational connections (in this case, just by connecting 'a' and 'c' to 0, and 'b' to 1).

 

The other type of assignment in VHDL is a signal assignment:

a <= '1'; 
b <= a;
a <= '0';
c <= a;

This does not behave how you might expect from C, because all of these assignments happen simultaneously. As a result, when the assignment "b <= a" occurs, "a <= 1" has not happened yet. "b" will take whatever value "a" had before this block was run. "c" will be in the same situation. "a" is actually set to both 1 and 0, and the language specification says that the later assignment wins. As a result, the final values here will be:

 

a = 0

b = <whatever "a" was before this block ran>

c = <whatever "a" was before this block ran>

 

 

If you do want sequential execution in VHDL or Verilog, you need to investigate how to build a state machine.

 

 

Also be wary of relying too much on the simulator. The simulator tends to implement VHDL or Verilog as-specified, which includes useful features like arbitrary delays. Many of these features cannot be implemented in hardware, and the synthesis tool will either ignore them (which tends to result in a lot of head-scratching) or throw an error.

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manoj_xilinx
Adventurer
Adventurer
3,055 Views
Registered: ‎11-22-2016

Thank you so much @florentw and @u4223374.

 

Appreciate your time.

 

Manoj

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