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bell_a
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Registered: ‎01-30-2018

[Project 1-486] Could not resolve non-primitive black box

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Hi! In vivado 2016.1 I generated an IP from the IP catalogue. Generated with parameter "Out of context per IP". But when the project is implemented, I have warning:

[Project 1-486] Could not resolve non-primitive black box cell 'dds' instantiated as 'uut/dds1' ["E:/project/project_15/project_15.srcs/sources_1/imports/new/test.v":42]

 

I already looked at topics with similar problems, but my problem did not solve anything. I'm new, please help me. 

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thakurr
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Registered: ‎09-15-2016

Hi @bell_a

 

So looks like this warning appears during regular synthesis run for which OOC synthesis netlist is blackbox, hence the warning. FYI both the netlists (regular as well as OOC) get combine in the opt design phase resolving the black boxes. This way implementation completes successfully.

So you can safely ignore this warning.

 

Regards

Rohit

Regards
Rohit
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thakurr
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Registered: ‎09-15-2016

Hi @bell_a

 

At what phase of design flow do you get this warning? Does your implementation completes successfully?

Please share the vivado.log located in the project directory.

 

Regards

Rohit

 

Regards
Rohit
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bell_a
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@thakurr
The warning appears after the synthesis is completed. At the same time, synthesis and implementation are completed without errors.

 

#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1733598 on Wed Dec 14 22:35:39 MST 2016
# IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
# Start of session at: Fri Feb 02 15:02:05 2018
# Process ID: 4580
# Current directory: E:/project/project_15
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent4400 E:\project\project_15\project_15.xpr
# Log file: E:/project/project_15/vivado.log
# Journal file: E:/project/project_15\vivado.jou
#-----------------------------------------------------------
start_gui
open_project E:/project/project_15/project_15.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2016.4/data/ip'.
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 787.500 ; gain = 169.602
reset_run fifo2_synth_1
reset_run synth_1
launch_runs synth_1 -jobs 2
INFO: [HDL 9-2216] Analyzing Verilog file "E:/project/project_15/project_15.srcs/sources_1/imports/new/test.v" into library work [E:/project/project_15/project_15.srcs/sources_1/imports/new/test.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "E:/project/project_15/project_15.srcs/sources_1/imports/new/top.v" into library work [E:/project/project_15/project_15.srcs/sources_1/imports/new/top.v:1]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo2'...
[Fri Feb 02 15:03:53 2018] Launched fifo2_synth_1...
Run output will be captured here: E:/project/project_15/project_15.runs/fifo2_synth_1/runme.log
[Fri Feb 02 15:03:53 2018] Launched synth_1...
Run output will be captured here: E:/project/project_15/project_15.runs/synth_1/runme.log
launch_runs impl_2 -jobs 2
[Fri Feb 02 15:05:47 2018] Launched impl_2...
Run output will be captured here: E:/project/project_15/project_15.runs/impl_2/runme.log
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7k160tfbg676-2
INFO: [Project 1-454] Reading design checkpoint 'e:/project/project_15/project_15.srcs/sources_1/ip/dds/dds.dcp' for cell 'uut/dds1'
INFO: [Project 1-454] Reading design checkpoint 'E:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2.dcp' for cell 'uut/fifo1'
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Device 21-403] Loading part xc7k160tfbg676-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [e:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2/fifo2.xdc] for cell 'uut/fifo1/U0'
Finished Parsing XDC File [e:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2/fifo2.xdc] for cell 'uut/fifo1/U0'
Parsing XDC File [E:/project/project_15/project_15.srcs/constrs_1/imports/new/cont.xdc]
Finished Parsing XDC File [E:/project/project_15/project_15.srcs/constrs_1/imports/new/cont.xdc]
INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'E:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2.dcp'
INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'e:/project/project_15/project_15.srcs/sources_1/ip/dds/dds.dcp'
Parsing XDC File [e:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2/fifo2_clocks.xdc] for cell 'uut/fifo1/U0'
INFO: [Timing 38-35] Done setting XDC timing constraints. [e:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2/fifo2_clocks.xdc:53]
get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1536.023 ; gain = 509.328
Finished Parsing XDC File [e:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2/fifo2_clocks.xdc] for cell 'uut/fifo1/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 2 instances

open_run: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1564.859 ; gain = 741.574
close_design
open_run impl_2
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.4
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [E:/project/project_15/.Xil/Vivado-4580-stud-5/dcp/top_early.xdc]
Finished Parsing XDC File [E:/project/project_15/.Xil/Vivado-4580-stud-5/dcp/top_early.xdc]
Parsing XDC File [E:/project/project_15/.Xil/Vivado-4580-stud-5/dcp/top.xdc]
Finished Parsing XDC File [E:/project/project_15/.Xil/Vivado-4580-stud-5/dcp/top.xdc]
Parsing XDC File [E:/project/project_15/.Xil/Vivado-4580-stud-5/dcp/top_late.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [E:/project/project_15/project_15.srcs/sources_1/ip/fifo2/fifo2/fifo2_clocks.xdc:60]
Finished Parsing XDC File [E:/project/project_15/.Xil/Vivado-4580-stud-5/dcp/top_late.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1629.473 ; gain = 0.027
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1629.473 ; gain = 0.027
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 2 instances

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thakurr
Moderator
Moderator
2,955 Views
Registered: ‎09-15-2016

Hi @bell_a

 

So looks like this warning appears during regular synthesis run for which OOC synthesis netlist is blackbox, hence the warning. FYI both the netlists (regular as well as OOC) get combine in the opt design phase resolving the black boxes. This way implementation completes successfully.

So you can safely ignore this warning.

 

Regards

Rohit

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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bell_a
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Registered: ‎01-30-2018
@thakurr, Thank you!
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