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574 Views
Registered: ‎01-30-2019

Query in verilog regarding use of always

Hello everyone,

I am designing ALU in Verilog and facing issues in always block. At the time of synthesis, I am getting the error and no error during syntax check and simulation. I have instantiated different modules in the ALU block.  Please tell me the correct way to use always statement.

Thanking you in advance.

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8 Replies
Teacher xilinxacct
Teacher
571 Views
Registered: ‎10-23-2018

Re: Query in verilog regarding use of always

singhkavita615@

you may want to post the code/errors/etc in context, so people may be able to see what you are seeing... It is a bit too vague to formulate meainingful reply to the specific 'issue'.

Hope that helps you get some replies

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557 Views
Registered: ‎01-30-2019

Re: Query in verilog regarding use of always

Here is my code

 

module alu(
input [15:0] input_1,input_2,
input [7:0] select,
output [31:0] result,
output carry_out
);

myand A1(.a(input_1), .b(input_2), .s(select), .out_1(result));
myor A2(.a(input_1), .b(input_2), .s(select), .out_2(result));
mynot A3(.a(input_1), .s(select), .out_3(result));
mynand A4(.a(input_1), .b(input_2), .s(select), .out_4(result));
mynor A5(.a(input_1), .b(input_2), .s(select), .out_5(result));
myxor A6(.a(input_1), .b(input_2), .s(select), .out_6(result));
myxnor A7(.a(input_1), .b(input_2), .s(select), .out_7(result));
increment_1 A8(.a(input_1), .s(select), .out_8(result));
decrement_1 A9(.a(input_1), .s(select), .out_9(result));
complement_1 A10(.a(input_1), .s(select), .out_10(result));
complement_2 A11(.a(input_1), .s(select), .out_11(result));
logical_left_shift A12(.a(input_1), .s(select), .out_12(result));
logical_right_shift A13(.a(input_1), .s(select), .out_13(result));
rotate_left A14(.a(input_1), .s(select), .out_14(result));
rotate_right A15(.a(input_1), .s(select), .out_15(result));
add A16(.a(input_1), .b(input_2), .s(select), .sum(result), .carry_1(carry_out));
subtract A17(.a(input_1), .b(input_2), .s(select), .diff(result), .carry_2(carry_out));
endmodule

module myand(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] out_1
);
always@(s, a, b)
begin
if(s == 'h00)
assign result = a&b;
deassign out_1;
end
endmodule

module myor(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] out_2
);
always@(s, a, b)
begin
if(s=='h01)
assign out_2 = a|b;
deassign out_2;

end
endmodule

module mynot(
input [15:0] a,
input [7:0] s,
output reg[31:0] out_3
);
always@(s, a)
begin
if(s=='h02)
assign out_3 = ~a;
deassign out_3;

end
endmodule

module mynand(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] out_4
);
always@(s, a, b)
begin
if(s=='h03)
assign out_4 = ~(a&b);
deassign out_4;

end
endmodule

module mynor(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] out_5
);
always@(s, a, b)
begin
if(s=='h04)
assign out_5 = ~(a|b);
deassign out_5;
end
endmodule

module myxor(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] out_6
);
always@(s, a, b)
begin
if(s=='h05)
assign out_6 = a^b;
deassign out_6;

end
endmodule

module myxnor(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] out_7
);
always@(s, a, b)
begin
if(s=='h06)
assign out_7 = a~^b;
deassign out_7;
end
endmodule

module increment_1(
input [15:0] a,
input [7:0] s,
output reg[31:0] out_8
);
always@(s, a)
begin
if(s=='h07)
assign out_8 = a+1;
deassign out_8;

end
endmodule

module decrement_1(
input [15:0] a,
input [7:0] s,
output reg[31:0] out_9
);
always@(s, a)
begin
if(s=='h08)
assign out_9 = a-1;
deassign out_9;

end
endmodule

module complement_1(
input[15:0] a,
input [7:0] s,
output reg[31:0] out_10
);
always@(s, a)
begin
if(s=='h09)
assign out_10 = ~a;
deassign out_10;

end
endmodule

module complement_2(
input[15:0] a,
input [7:0] s,
output reg[31:0] out_11
);
always@(s, a)
begin
if(s=='h0A)
assign out_11 = ~a +1;
deassign out_11;
end
endmodule

module logical_left_shift(
input [15:0] a,
input [7:0] s,
output reg[31:0] out_12
);
always@(s, a)
begin
if(s=='h0B)
assign out_12 = a<<1;
deassign out_12;
end
endmodule

module logical_right_shift(
input [15:0] a,
input [7:0] s,
output reg[31:0] out_13
);
always@(s, a)
begin
if(s=='h0C)
assign out_13 = a>>1;
deassign out_13;
end
endmodule

module rotate_left(
input[15:0] a,
input [7:0] s,
output reg[31:0]out_14
);
always@(s, a)
begin
if(s=='h0D)
assign out_14 = {a[14:0],a[15]};
deassign out_14;

end
endmodule

module rotate_right(
input[15:0] a,
input [7:0] s,
output reg[31:0] out_15
);
always@(s, a)
begin
if(s=='h0E)
assign out_15 = {a[0],a[15:1]};
deassign out_15;
end
endmodule

module add(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] sum,
output reg carry_1
);
always@(s, a, b)
begin
if(s=='h0F)
assign {carry_1,sum} = a + b;
deassign {carry_1,sum};
end
endmodule

module subtract(
input [15:0] a,b,
input [7:0] s,
output reg[31:0] diff,
output reg carry_2
);
always@(s, a, b)
begin
if(s=='h10)
assign {carry_2,diff} = a + (~b +1);
deassign {carry_2,diff};
end
endmodule

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Teacher xilinxacct
Teacher
539 Views
Registered: ‎10-23-2018

Re: Query in verilog regarding use of always

singhkavita615@

There may be some other problems (Check the messages in the message tab)... I didn't get as far as seeing anything with 'always'... but I do see ....

You have used assign statement in a procedural block making it a procedural continuous assignment. (that is not supported as synthsizable in Vivado). Look at removing the 'assign' in such a context.

Hope that helps

If so, Please mark as solution accepted. Kudos also welcomed. :-)

Contributor
Contributor
533 Views
Registered: ‎10-25-2018

Re: Query in verilog regarding use of always

singhkavita615@

Check out the Vivado Synthesis guide, which states "Vivado synthesis does not support assign and deassign statements." (Page 251 in the 2018.3 edition)

Also, your code looks like it's straight out of 1996. There have been many improvements to Verilog / SystemVerilog since then. Not needing a sensitivity list for combinational blocks being one of them.

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487 Views
Registered: ‎01-30-2019

Re: Query in verilog regarding use of always

I am synthesising my code on ISE software and simulation on Xilinx.

There is no error message in my code during simulation. The only error during synthesis is the continuous procedural assignment.

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Scholar u4223374
Scholar
385 Views
Registered: ‎04-26-2015

Re: Query in verilog regarding use of always

As above, you're using some features that are not supported in synthesis.

 

The simulator generally accepts anything that's valid Verilog. However, not all Verilog can actually be synthesized.

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321 Views
Registered: ‎01-30-2019

Re: Query in verilog regarding use of always

Please help me in synthesising the code, as I have to calculate area, power and delay.

Else suggest me some another way to do this, or some book from where I can get the help.

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Teacher xilinxacct
Teacher
310 Views
Registered: ‎10-23-2018

Re: Query in verilog regarding use of always

singhkavita615@

If you want to calculate the area etc... as mentioned by all of the above, you need to use only sythesizable portions of the language. Once you do that, all is well.

Using 'non-sythesizable' code is completely valid (and primarily intended only in a test bench), so during synthesis, it will not generate a warning. It will only warn when using in code that is trying to be targeted as real hardware (e.g. implementation).

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. 

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