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Observer
Observer
14,766 Views
Registered: ‎11-26-2014

Question about --synthesis translate_on and translate_off

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Hello all,

 

I am porting a project from Spartan-3A to Spartan-6 in ISE 13.4. When using the bbfifo_16x8.vhd (original from 2003) in the Spartan-6 project, I did have to remove the INIT attributes, because ISE was giving an error in those lines, but after that, I realized that ISE wasn't synthesizing this block. After looking for a reason in google, I got a 2010 version of bbfifo_16x8.vhd from Ken Chapman, where it appears a comment saying:

 

 

 

-- Version : 1.20 
-- Version Date : 11th December 2006
-- Reason : Attributes and '--translate on/off' directives removed as no longer 
--          required for XST.

 

 

 

My question is, why are this directives no longer supported? Why is it that the original source code worked for Spartan-3A and does not work for Spartan-6?

 

 

Thank you very much,

 

Lucky

 

 

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Moderator
Moderator
24,301 Views
Registered: ‎06-24-2015

Re: Question about --synthesis translate_on and translate_off

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Hi,

 

TRANSLATE_OFF and TRANSLATE_ON instructs the Synthesis tool to ignore blocks of code. 

This can be useful to ignore source code that is not relevant for Synthesis, such as simulation code. 

These attributes are given within a comment in RTL code. The comment should start with one of the following keywords:

  • synthesis
  • synopsys
  • pragma

TRANSLATE_OFF starts the section of code to be ignored, and TRANSLATE_ON ends the section to be ignored. These attributes cannot be nested.

Be careful with the types of code that are included between the translate statements. 

If it is code that affects the behavior of the design, a simulator could use that code, and create a simulation mismatch.

Verilog Example

// synthesis translate_off

...Code to be ignored...

// synthesis translate_on

VHDL Example

-- synthesis translate_off

...Code to be ignored...

-- synthesis translate_on

------------------------------------------------------------------------------------------------------------

Give kudos if it led you to the solution, accept as solution if it resolved your query.

 

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).

View solution in original post

3 Replies
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Moderator
Moderator
24,302 Views
Registered: ‎06-24-2015

Re: Question about --synthesis translate_on and translate_off

Jump to solution

Hi,

 

TRANSLATE_OFF and TRANSLATE_ON instructs the Synthesis tool to ignore blocks of code. 

This can be useful to ignore source code that is not relevant for Synthesis, such as simulation code. 

These attributes are given within a comment in RTL code. The comment should start with one of the following keywords:

  • synthesis
  • synopsys
  • pragma

TRANSLATE_OFF starts the section of code to be ignored, and TRANSLATE_ON ends the section to be ignored. These attributes cannot be nested.

Be careful with the types of code that are included between the translate statements. 

If it is code that affects the behavior of the design, a simulator could use that code, and create a simulation mismatch.

Verilog Example

// synthesis translate_off

...Code to be ignored...

// synthesis translate_on

VHDL Example

-- synthesis translate_off

...Code to be ignored...

-- synthesis translate_on

------------------------------------------------------------------------------------------------------------

Give kudos if it led you to the solution, accept as solution if it resolved your query.

 

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).

View solution in original post

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Moderator
Moderator
14,751 Views
Registered: ‎06-24-2015

Re: Question about --synthesis translate_on and translate_off

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In ISE Design Suite 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families.

The new parser brings a lot of improvements to the XILINX Synthesis solution.

However, several constructs supported in the XST Standard version for older FPGA families (such as Virtex-5 and Spartan-3) are not VHDL/Verilog LRM compliant.

Some of them are rejected by the new parser and some of them are interpreted differently.

Such situations will require some VHDL/Verilog code changes to successfully process the design using the new parser.

Also, refer to following Answer Records:
http://www.xilinx.com/support/answers/32927.html
http://www.xilinx.com/support/answers/32974.html
Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
Highlighted
Observer
Observer
14,737 Views
Registered: ‎11-26-2014

Re: Question about --synthesis translate_on and translate_off

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Thank you very much for your invaluable help!

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