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Visitor
Visitor
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Registered: ‎06-28-2020

Question regarding BRAM inferrence

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Hi,

I have tried creating some BRAM using VHDL. The data width is 8 bits. I have tried varying the address width to see what the Vivado synthesized design looks like each time. Here is what I see:

  • Address width is 13 bits => two RAMB36 blocks used (ADDRARDADDR[15:0], DOADO[31:0])
  • Address width is 12 bits => one RAMB36 block used (ADDRARDADDR[15:0], DOADO[31:0])
  • Address width is 11 bits => one RAMB18 block used (ADDRARDADDR[13:0], DOADO[15:0])

I don't understand what is going on here. How can RAMB18 have address width 14 and data width 16. Does this not equate to 2^14 * 2 bytes = 32Kb? But then if this is the case, why is one RAMB18 block not used when I set my address width to 12 or 13?

Thanks for any help.

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Xilinx Employee
Xilinx Employee
479 Views
Registered: ‎07-21-2014

Hi @zomby99 ,

RAMB18 primitive has ADDRARDADDR width of 14 bits to facilitate RAM inference of size 16Kx1(16Kb). And data width of [15:0] to allow RAM inference of size 1Kx16 (16Kb).
In your case, data width is 8 bit and address width is 11 bits, which makes RAM of size- 2^11x8= 2kx8 bit(16Kb).
Address bits used in this case are ADDRARDADDR[13:3] and rest of this bits are connected to const_1.
Databits used are DOADO[7:0] and rest of the bits are unconnected.

Similarly when address width is 12 and data width is 8, RAM size is 2^12x8 = 4Kx8 (32Kb). Which requires one RAMB36 and so on.

 

-Shreyas

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Adventurer
Adventurer
538 Views
Registered: ‎05-19-2014

The BRAM primitives have extra address bits that facilitate the further partitioning of the datapath into 9-, 4-, 2- or even 1-bit words. If you have 16-bit data words, these additional address bits go unused. The internal data multiplexers controlled by these bits are not used. So, your real address space is not 2^14.

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Voyager
Voyager
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Registered: ‎06-20-2012

The Xilinx Memory Resources user guide shows all the possible block RAM configurations.

== If this was helpful, please feel free to give Kudos, and close if it answers your question ==
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Xilinx Employee
Xilinx Employee
480 Views
Registered: ‎07-21-2014

Hi @zomby99 ,

RAMB18 primitive has ADDRARDADDR width of 14 bits to facilitate RAM inference of size 16Kx1(16Kb). And data width of [15:0] to allow RAM inference of size 1Kx16 (16Kb).
In your case, data width is 8 bit and address width is 11 bits, which makes RAM of size- 2^11x8= 2kx8 bit(16Kb).
Address bits used in this case are ADDRARDADDR[13:3] and rest of this bits are connected to const_1.
Databits used are DOADO[7:0] and rest of the bits are unconnected.

Similarly when address width is 12 and data width is 8, RAM size is 2^12x8 = 4Kx8 (32Kb). Which requires one RAMB36 and so on.

 

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

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Visitor
Visitor
414 Views
Registered: ‎06-28-2020

@aher Thank you for taking the time to explain so clearly.

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