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Registered: ‎01-01-2019

Questions about Synth 8-3917:WARNING: [Synth 8-3917] design rxd_autocor__GB39 has port P[1] driven by constant 0

`timescale 1ns / 1ps
module rxd_autocor(
        input clk,
        input rst,
        input read_finish,  
	input enable_cor,   
	output reg cor_finish,  
	output reg enable_read,           
        input signed [31:0] reg_all_0,  
        input signed [31:0] reg_all_1,  
        input signed [31:0] reg_all_2,    
	input signed [31:0] reg_all_3,     
	input signed [31:0] reg_all_4,     
	input signed [31:0] reg_all_5,    
	input signed [31:0] reg_all_6,   
	input signed [31:0] reg_all_7,   
	input signed [31:0] reg_all_8,   
	input signed [31:0] reg_all_9,   
	input signed [31:0] reg_all_10,  
	input signed [31:0] reg_all_11,   
	input signed [31:0] reg_all_12,   
	input signed [31:0] reg_all_13,   
	input signed [31:0] reg_all_14,    
	input signed [31:0] reg_all_15,  
	input signed [31:0] reg_all_16,  
	input signed [31:0] reg_all_17,
        input signed [31:0] reg_all_18,  
	input signed [31:0] reg_all_19,  
	output reg flag_cor_finish,
	output reg [63:0] dina, 
	output reg ena,
	output reg wea, 
	output reg [8:0] addra_in);
    
        reg signed [31:0] reg_all[19:0];   
        reg [3:0] case_cor2read;
        reg [14:0] cnt_cor;                  
    
        reg signed [63:0] R_add0 [19:0];   
	reg signed [63:0] R_add1 [19:0];   
	reg signed [63:0] R_add2 [19:0];    
	reg signed [63:0] R_add3 [19:0];   
	reg signed [63:0] R_add4 [19:0];   
	reg signed [63:0] R_add5 [19:0];   
	reg signed [63:0] R_add6 [19:0];   
	reg signed [63:0] R_add7 [19:0];   
	reg signed [63:0] R_add8 [19:0];    
	reg signed [63:0] R_add9 [19:0];    
	reg signed [63:0] R_add10 [19:0];   
	reg signed [63:0] R_add11 [19:0]; 
	reg signed [63:0] R_add12 [19:0];  
	reg signed [63:0] R_add13 [19:0];   
	reg signed [63:0] R_add14 [19:0];   
	reg signed [63:0] R_add15 [19:0];  
	reg signed [63:0] R_add16 [19:0];  
	reg signed [63:0] R_add17 [19:0];
        reg signed [63:0] R_add18 [19:0];  
	reg signed [63:0] R_add19 [19:0];
	reg signed [63:0] R_mult[19:0];
        reg [6:0] cnt_Rmul;   
        reg [13:0] cnt_input;
        reg [6:0] cnt_in_cor;
        reg signed [63:0] R_cor[399:0];

I have created a new project .Its ports and registers are presented in the code. When I synthesis this project, the following warnings appeared.

WARNING: [Synth 8-3917] design rxd_autocor__GB39 has port P[1] driven by constant 0
WARNING: [Synth 8-3917] design rxd_autocor__GB39 has port P[0] driven by constant 0

I'm sure I do not define any ports or regs named GB39.  I found warnings and GB39 appears in the file under this path: project.runs/synth_1/project.vds.

Report RTL Partitions: 
+------+--------------------------+------------+----------+
|      |RTL Partition             |Replication |Instances |
+------+--------------------------+------------+----------+
|1     |rxd_autocor__GB0          |           1|     27216|
|2     |rxd_autocor__GB1          |           1|      9393|
|3     |rxd_autocor__GB2          |           1|     10359|
|4     |rxd_autocor__GB3          |           1|     15947|
|5     |rxd_autocor__GB4          |           1|     17849|
|6     |rxd_autocor__GB5          |           1|     27530|
|7     |rxd_autocor__GB6          |           1|      8380|
|8     |rxd_autocor__GB7          |           1|     30445|
|9     |rxd_autocor__GB8          |           1|     34257|
|10    |rxd_autocor__GB9          |           1|     21252|
|11    |rxd_autocor__GB10         |           1|     13730|
|12    |rxd_autocor__GB11         |           1|     34692|
|13    |rxd_autocor__GB12         |           1|      9003|
|14    |rxd_autocor__GB13         |           1|     10888|
|15    |rxd_autocor__GB14         |           1|     24479|
|16    |rxd_autocor__GB15         |           1|     15310|
|17    |rxd_autocor__GB16         |           1|     15355|
|18    |muxpart__1139_rxd_autocor |           1|     25541|
|19    |rxd_autocor__GB18         |           1|     21021|
|20    |rxd_autocor__GB19         |           1|     27022|
|21    |rxd_autocor__GB20         |           1|     33934|
|22    |rxd_autocor__GB21         |           1|      9844|
|23    |rxd_autocor__GB22         |           1|     13920|
|24    |rxd_autocor__GB23         |           1|     14280|
|25    |rxd_autocor__GB24         |           1|     17948|
|26    |rxd_autocor__GB25         |           1|     22547|
|27    |rxd_autocor__GB26         |           1|     29778|
|28    |rxd_autocor__GB27         |           1|     23477|
|29    |rxd_autocor__GB28         |           1|     19339|
|30    |rxd_autocor__GB29         |           1|     13892|
|31    |rxd_autocor__GB30         |           1|     16915|
|32    |rxd_autocor__GB31         |           1|     19582|
|33    |rxd_autocor__GB32         |           1|     33866|
|34    |rxd_autocor__GB33         |           1|      8824|
|35    |rxd_autocor__GB34         |           1|     21504|
|36    |rxd_autocor__GB35         |           1|     19456|
|37    |rxd_autocor__GB36         |           1|     10368|
|38    |rxd_autocor__GB37         |           1|     17110|
|39    |rxd_autocor__GB38         |           1|     19582|
|40    |rxd_autocor__GB39         |           1|     26219|
|41    |rxd_autocor__GB40         |           1|     33417|
|42    |rxd_autocor__GB41         |           1|     12006|
|43    |rxd_autocor__GB42         |           1|     13119|
|44    |rxd_inv__GB0              |           1|   3433482|
|45    |rxd_top__GC0              |           1|       252|
+------+--------------------------+------------+----------+

I can't determine what GB39 stands for, so I can't locate which port is driven by constant 0. 

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1 Reply
Xilinx Employee
Xilinx Employee
244 Views
Registered: ‎05-14-2008

Re: Questions about Synth 8-3917:WARNING: [Synth 8-3917] design rxd_autocor__GB39 has port P[1] driven by constant 0

Is the module rxd_autocor used several times in your design?

The __GBxx is the postfix added by the tool when a instance is used more than once in the design.

The port P mentioned in the message might be an intermediate port named by the tool when optimizations are done across the hierarchy boundary and the hierarchy is rebuilt. 

Optimization like this is common in Synthesis and does not always indicate an issue in code. Usually you don't need to care much about this kind of warning, unless you see significant unusual resource utilization or malfunction related to the module mentioned, especially when your code passes simulation.

Setting -flatten_hierarchy to none can be a way to analyze this issue if you like. As in this way, the hierarchy boundary will not be changed and you will likely not see any port name in the message that does not exist in your code.

-vivian

 

 

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