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Newbie chen18wijn@
Newbie
712 Views
Registered: ‎08-06-2018

RAM_MODE attributes

Hi,
I would like to know if there’s a way to infer a Block RAM as SDP using attributes. In the document UG473 page 35 it says specifically that there are attributes for this purpose, but I couldn’t find an example for that.
Thank you.
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3 Replies
Moderator
Moderator
694 Views
Registered: ‎11-04-2010

Re: RAM_MODE attributes

You can refer to "RAM_STYLE" attribute in UG901.
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Moderator
Moderator
660 Views
Registered: ‎07-21-2014

Re: RAM_MODE attributes

chen18wijn@

 

I believe the UG473 is discussing the primitive based attributes and not the RTL inference based primitives:

RAM_MODE.PNG

Above snapshot was taken from language template of Vivado. 

 

In RTL you can guide the tool by using RAM_STYLE whether you want to infer BRAM or not, and based on RTL description and read-write structure, synthesis engine will infer the memory as SDP/TDP.

 

Thanks

Anusheel 

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654 Views
Registered: ‎01-22-2015

Re: RAM_MODE attributes

Hi chen18wijn@

 

Welcome to the Xilinx Forum!

 

Xilinx document UG473 mostly discusses use of the RAM primitives (RAMB36E1 and RAMB18E1) to get block-RAM into your project.  This is not a very popular method.

 

Another way to get block-RAM (SDP in your case) is to infer it using the code examples found on pages pages 117-120 of Xilinx document UG901.  You can simply copy the code examples from UG901 into your project  -or-  on page 110 of UG901, you will find a link called "Coding Examples" that enables you to download the file, ug901-vivado-synthesis-examples.zip, with the code examples.

 

Finally, you can get block-RAM by using the Xilinx IP called the Block Memory Generator that is described by Xilinx document PG058.

 

In most cases, I prefer to infer block-RAM using the UG901 coding examples - since this helps keep my code portable.

 

Cheers,

Mark