08-06-2018 02:01 PM
08-06-2018 04:27 PM
08-07-2018 04:15 AM
I believe the UG473 is discussing the primitive based attributes and not the RTL inference based primitives:
Above snapshot was taken from language template of Vivado.
In RTL you can guide the tool by using RAM_STYLE whether you want to infer BRAM or not, and based on RTL description and read-write structure, synthesis engine will infer the memory as SDP/TDP.
08-07-2018 05:02 AM
Welcome to the Xilinx Forum!
Xilinx document UG473 mostly discusses use of the RAM primitives (RAMB36E1 and RAMB18E1) to get block-RAM into your project. This is not a very popular method.
Another way to get block-RAM (SDP in your case) is to infer it using the code examples found on pages pages 117-120 of Xilinx document UG901. You can simply copy the code examples from UG901 into your project -or- on page 110 of UG901, you will find a link called "Coding Examples" that enables you to download the file, ug901-vivado-synthesis-examples.zip, with the code examples.
Finally, you can get block-RAM by using the Xilinx IP called the Block Memory Generator that is described by Xilinx document PG058.
In most cases, I prefer to infer block-RAM using the UG901 coding examples - since this helps keep my code portable.