08-06-2018 09:22 PM - edited 08-06-2018 09:37 PM
I got some source code about TDC from "Free Software Foundation, Inc", and modified some code to migrate from Spartan 6 to Ultrascale device. During this process, I met several problem.
Attachments are the source code I have maken some change.
In my project, I pass the U_SET and RLOC parameters from top file to the bottom file. The U_SET and RLOC are directly applied to the CARRY8 cell. The location of CARRY8s is shaped to a column first, it didn't work. Then I constrain the CARRY8s to a rectangle, it didn't work.
In the 20180807122111.png, the red cells are SAMPLER2, yellow cells are SAMPLER1.
It seem that the constrains do not work at all.
BTW, Vivado version is 2017.4.
08-08-2018 07:26 PM
Nobody answer this question........
I made a little change(CARRY8 to CARRY4) and implemented the delay chain in V7 series device today. In V7 device, the constrain worked well.
What makes the different result between 7 series device and Ultrascale?
08-09-2018 02:30 AM
A lot of library and Xilinx primitive differences exist b/w series6, series7 and Ultrascale devices.
I think these should be manually replaced during RTL porting to avoid errors.
08-09-2018 07:08 PM
Yes, primitives may be different from series to series. I checked the primitives which I instantiated in my project, they were all correct.
I have solved the problem.
When I implemented my project(with proper modified code) in V7 devices, the RLOC worked well without any other constrains.
But when I implemented my project in Ultrascale devices, the RLOC never worked if I used it alone. Users should create a PBLOCK first, and then place the cells with RLOC constrains in it. This time, all the CARRY8 cells aligned according to the RLOC.
Why the RLOC works differently between V7 devices and Ultrascale devices?