cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
gherbome
Visitor
Visitor
508 Views
Registered: ‎04-15-2021

RTL Analysis doesn't match with synthesis schematic

Hi, i'm french student and i try to program a spi component. I experience a problem. When i open the schematic of the synthesis. The schematic show something strange. I'm supposed to have 4 outputs  but on the schematic there are only one output.

You can find my code on the SPI2.zip

The aim of this project is to set register on a component maned SSD2828 in order to generate MIPI DSI signal. I'm a beginner and i really can't find my issue

 

Thanks you

fpga_rtl_synthesis.pngfpga_synthesis_schematic.pngfpga_simulation_spi.pnghave 

 

0 Kudos
11 Replies
drjohnsmith
Teacher
Teacher
498 Views
Registered: ‎07-09-2009

There are a few bits ot get into here,

   The simulation of your code, does just that , it simulates your code as written,

     its up to your test bench to test the code then

Once synthesised, and then place and routed, 

    your code is optimised, none used bits removed, and then the tools try to fit your design into the available logic to meet your constraints,

      It similar to you write C code, and that gets optimised into ASM, using all sorts of parallel and time shift bits.

           i.e. the ASM looks nothing like your C code.

The place to find errors is the simulator, not the schematic view.

   once simulated Ok, then you put constraints on, 

     and synthesise, 

         then you look at the warnings from the synthesis to see if it went ok,

then you either dump it into the fpga, or you do a post PAR simulation,

Th eonly real use of the schematics ( IMHO ) is if your coding to get say a SLR and you look at the report file and find it has not made a SLR, 

     then you can try to decipher

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
gherbome
Visitor
Visitor
480 Views
Registered: ‎04-15-2021

Thanks you for your answers

But when i try on my zybo z7 for example the mosi_spi_o signal doesn't change and this is not what is expect. So how to find the problem if the simulation look like good and there are issue message. It's possible to debug when the fpga is programmed to look where is the issue ?

0 Kudos
drjohnsmith
Teacher
Teacher
460 Views
Registered: ‎07-09-2009

The  zybo z7  is an arm processor board with fpga built in,

You mention mesage ,

   is this SPI on the PL or the PS side ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
gherbome
Visitor
Visitor
442 Views
Registered: ‎04-15-2021

I dont know what is PL and PS. I find on google PL = Logic Programmable and PS = Processing System. So my message mention PL because i want to create from vhdl and verilog.

I just want create a component able to generate MOSI, CS, CLK when i press button

 

Thank you again for your help

0 Kudos
drjohnsmith
Teacher
Teacher
408 Views
Registered: ‎07-09-2009

Ok, 

so its the FPGA side, the PL, 

   not C code. 

Its just the PS side also has SPI ports, was wondering if you were tryign to use them ,

what's your experience of this board and writing code for the FPGA side of the device ?

   what are you using for the clock on the PL side 

 Have you done anything like get a led to light form the PL side ?

Im just trying to explore what we have as a common we know works, so we can debug ,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
gherbome
Visitor
Visitor
329 Views
Registered: ‎04-15-2021

For the clock i using the L16 pin which provide a frequency of 125 Mhz. Yes i able to light a led. Last time i made frequency divider and i succed to load on the board. 

Currently with my code, when i click on the button0, the led 0 is on same for button1 and the led 1. I'm able to watch the clock divided by 50 on a scope

0 Kudos
drjohnsmith
Teacher
Teacher
311 Views
Registered: ‎07-09-2009

Thats a great start

So then ,

   out with scope, probe the IO pins, see what they are doing ?

you said right at the beginning that you had only one output , you were expecting 4, as you have seen in the simulation,

   when you synthesised and P&R , did you get any errors / warnings ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
arora2deepak
Newbie
Newbie
310 Views
Registered: ‎04-16-2021

I dont know what is PL and PS. I find on google PL = Logic Programmable and PS = Processing System. So my message mention PL because i want to create from vhdl and verilog.
0 Kudos
drjohnsmith
Teacher
Teacher
307 Views
Registered: ‎07-09-2009

I htought we discussed this , sorry  ,

 

yes PL is program logic, PS is ARM side

    You mention L16 as the clock , thats going into the FPGA PL side ?

       I mention as the PS often used to provides the clocks for the PL side, though it does not have to .

 

its easier to put the clock in to the FPGA yourslef,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
gherbome
Visitor
Visitor
190 Views
Registered: ‎04-15-2021

The L16 is a clock because the zybo card provide 125Mhz clock. ( https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual chaper 12: Clock source)

Can i use L16 ? I need to use PS to provide clock ? 

Can you add more explication about : "its easier to put the clock in to the FPGA yourself" ? If i put clock by myself what is the clock generator ?

0 Kudos
drjohnsmith
Teacher
Teacher
174 Views
Registered: ‎07-09-2009

I was referring to the ease of using the PS side clock on the PL compared to using your own clock 

Sorry I dont know your board,

  Does L16 go to a MMCM / PLL of the FPGA Pl side or is that into the PS side. 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos