UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
2,127 Views
Registered: ‎04-29-2010

RTL error or possible issue with Vivado 2017.3 ?

Hi,
Here is my simple piece of code. It is basically an array assignment in VHDL.
Any idea why the same piece of code, behaves very differently, when it is coded slightly different ?!
Is this possibly an issue with Vivado 2017.3 ? Or something wrong with the assignment operation?

 

I believe all the three piece of code should've behaved exactly the same!!!

 

Here is my signal declaration:

 

constant INPUT_WIDTH  : integer := 10;
constant PARALLEL_COUNT  : integer := 8;

subtype input_t is signed(INPUT_WIDTH-1 downto 0);
type input_array_t is array(PARALLEL_COUNT-1 downto 0) of input_t;
signal in_array         : input_array_t := (others => (others => '0'));
signal out_array        : input_array_t := (others => (others => '0'));

 

 

 

The following code compiles with no warning and simulates just fine:

 

forward_p : process(clk)
begin
    if rising_edge(clk) then
            for n in 0 to PARALLEL_COUNT-1 loop
                out_array(n) <= in_array(n); 
            end loop;
    end if;
end process;

 

 

 

The following code compiles with no warning, but does NOT simulate, and simulator errors out:

 

forward_p : process(clk)
begin
    if rising_edge(clk) then
            for n in 0 to 7 loop
                out_array(n) <= in_array(n); 
            end loop;
    end if;
end process;

ERROR: [Simulator 45-1] A fatal run-time error was detected.  Simulation cannot continue.

 

 

 

 

The following code, errors out during the elaboration stage: 

 

forward_p : process(clk)
begin
    if rising_edge(clk) then
            out_array(0) <= in_array(0);
            out_array(1) <= in_array(1); 
            out_array(2) <= in_array(2); 
            out_array(3) <= in_array(3); 
            out_array(4) <= in_array(4); 
            out_array(5) <= in_array(5); 
            out_array(6) <= in_array(6); 
            out_array(7) <= in_array(7); 
    end if;
end process;

 

WARNING: [VRFC 10-923] index value <1> is out of range [0:0] of array <in_array>
WARNING: [VRFC 10-916] index 1 is out of array constraint 0 downto 0 for target out_array
WARNING: [VRFC 10-923] index value <2> is out of range [0:0] of array <in_array>
WARNING: [VRFC 10-916] index 2 is out of array constraint 0 downto 0 for target out_array
WARNING: [VRFC 10-923] index value <3> is out of range [0:0] of array <in_array>
WARNING: [VRFC 10-916] index 3 is out of array constraint 0 downto 0 for target out_array
WARNING: [VRFC 10-923] index value <4> is out of range [0:0] of array <in_array>
WARNING: [VRFC 10-916] index 4 is out of array constraint 0 downto 0 for target out_array
WARNING: [VRFC 10-923] index value <5> is out of range [0:0] of array <in_array>
WARNING: [VRFC 10-916] index 5 is out of array constraint 0 downto 0 for target out_array
WARNING: [VRFC 10-923] index value <6> is out of range [0:0] of array <in_array>
...
ERROR: [XSIM 43-3952] Index out of range for target out_array.

 

 

 

Thanks, 

--Rudy 

 

 

 

0 Kudos
16 Replies
2,102 Views
Registered: ‎03-27-2014

Re: RTL error or possible issue with Vivado 2017.3 ?

that's maybe because you are declaring a custom type using another custom type. I'm not saying that's not doable, I have never seen it before, but as long as syntax is OK it should work, right? (-_-) I also tend to make things easy for HDL implementation tools because they're basically a pain to work with.

 

I would rather declare

 

type input_array is array(PARALLEL_COUNT-1 downto 0) of signed(INPUT_WIDTH-1 downto 0);

the "n to N-1" (soft encoding) vs "n to 7" (hard encoding) issue is funny, but once again, I just dont trust Vivado/ISE or pretty much any error message it can give you, because previous warnings/errors can induce misleading fatal warnings/errors.

 

one last thing, I would rather code N processes (describe N registers) instead of calling "loop" (<-- which I just don't trust) within one register, like you did in the last example. Because my way is closer to a machine friendly thing, than your way would seem to require to much of a smart routing/interprating tool. Once again I just don't trust the tool.  

G.W.,
NIST - Time Frequency metrology
0 Kudos
2,094 Views
Registered: ‎01-22-2015

Re: RTL error or possible issue with Vivado 2017.3 ?

-just a minor note on style.

 

I think that

forward_p : process(clk)
begin
   .....
end process forward_p;

is preferable to

 

forward_p : process(clk)
begin
   .....
end process;
Explorer
Explorer
2,065 Views
Registered: ‎04-29-2010

Re: RTL error or possible issue with Vivado 2017.3 ?

Any suggestion from Xilinx folks?

Because I honestly don't see anything wrong with my code.

Any idea why Vivado 2017.3 Simulator behaves this way? This is a very simple array assignment, and it should definitely work. 

 

 

 

 

 

0 Kudos
2,030 Views
Registered: ‎01-22-2015

Re: RTL error or possible issue with Vivado 2017.3 ?

@rudy

 

The attached project was created using Vivado v2017.3 to test the VHDL you have shown.  I find that no errors or warnings are produced during synthesis or simulation.   Please note that:

 

  • ug901 has examples of what you are doing
  • I use IEEE.NUMERIC_STD.ALL to make the signed type available
  • I am specifying that my files are “VHDL” and not “VHDL 2008”

Cheers,

Mark

 

 

 

0 Kudos
Explorer
Explorer
2,018 Views
Registered: ‎04-29-2010

Re: RTL error or possible issue with Vivado 2017.3 ?

markg@prosensing.com 

Thanks, I ran the attached project, and yes that works fine. However, my simple project is also very similar to yours and very simple, and I am calling all the libraries that you specified, YET I am getting the errors as I described. So, something must not be right. And, I just to make it even simpler, I disconnected all the input and output ports that are driving or being driven by "in_array" and "out_array". And I am not using them anywhere else. So, basically, no where else in my test, I am using "in_array" and "out_array"...! And yet it doesn't work. 

Thanks for creating the test project, and I see it works there. But there has to be something wrong with it...

 

--Rudy 

0 Kudos
1,941 Views
Registered: ‎01-22-2015

Re: RTL error or possible issue with Vivado 2017.3 ?

@rudy

 

      ...I disconnected all the input and output ports that are driving or being driven by "in_array" and "out_array".

Be careful!   Normally, this “disconnect” will cause synthesis to produce nothing – unless you put DONT_TOUCH on "in_array" and "out_array" – as I did.

 

If you want, archive your test project and attach it to this post.   I will try running it on my computer.

 

Cheers,

Mark

0 Kudos
Explorer
Explorer
1,929 Views
Registered: ‎09-07-2011

Re: RTL error or possible issue with Vivado 2017.3 ?

Double check the PARALLEL_COUNT constant. It is as if it is 1 and not 8.

If you do a manual for loop is 0 to 0 does it not complain?

Could check that :

Assert parallel_count = 8
Assert in_array’length = 8

Etc.
0 Kudos
Explorer
Explorer
1,919 Views
Registered: ‎04-29-2010

Re: RTL error or possible issue with Vivado 2017.3 ?

markg@prosensing.com

Thanks, but I really cannot attach the project, since there are other codes in there. So, I wrote a small test bench to test out this issue in a big project. But my main project has hundreds of other modules. 

0 Kudos
Explorer
Explorer
1,917 Views
Registered: ‎04-29-2010

Re: RTL error or possible issue with Vivado 2017.3 ?

@geoffbarnes

It is actually 8. 

issue.png

0 Kudos
Explorer
Explorer
1,500 Views
Registered: ‎09-07-2011

Re: RTL error or possible issue with Vivado 2017.3 ?

Weird, the tool is saying that in_array and out_array have range [0:0]..  

 

Wouldn't hurt to check :

 

forward_p : process(clk)
begin
    if rising_edge(clk) then

            assert PARALLEL_COUNT = 8  report "oops not 8??"                          severity ERROR;

            assert in_array'length           = 8  report "oops array length problem??" severity ERROR;

            for n in 0 to PARALLEL_COUNT-1 loop
                out_array(n) <= in_array(n);
            end loop;
    end if;
end process;

 

 

0 Kudos
Explorer
Explorer
1,469 Views
Registered: ‎09-07-2011

Re: RTL error or possible issue with Vivado 2017.3 ?

Hard to say if there's a bug at the root of things, but for your last two code examples it is not unexpected that one is a run-time error and the other an elaboration error.    Just a side effect of coding style.

 

 

Like this:

 

entity foo is
port (
	ELAB_ERROR    : out bit;
	RUNTIME_ERROR : out bit
);
end entity;
architecture test of foo is
	constant A : bit_vector(0 to 0) := "0";
begin
	process
	begin
		ELAB_ERROR <= A(1); -- xelab error
		for k in 1 to 1 loop
			RUNTIME_ERROR <= A(k);  -- xsim error
end loop; wait; end process; end architecture

 

 

0 Kudos
1,450 Views
Registered: ‎01-22-2015

Re: RTL error or possible issue with Vivado 2017.3 ?

@rudy

Did you recently auto-upgrade your project from an old version of Vivado to v2017.3 – and then begin to see the problem?

 

If so, you might want to try a “fresh start” approach to the project upgrade.  That is, create a new blank project in v2017.3.  Import the constraints file and VHDL files that you wrote from the old project.   Then (and most importantly), create and manually reconfigure each of your IP.  That is, do not simply import the IP .xci files from the old project.

 

I know that upgrading Vivado and IP seems to be a weird connection to the problem you are seeing. -but, it is a weird problem. Maybe two weirds make a right?

 

Mark

0 Kudos
Explorer
Explorer
1,378 Views
Registered: ‎04-29-2010

Re: RTL error or possible issue with Vivado 2017.3 ?

I opened a case with Xilinx team, but I haven't heard anything yet..... 

They told me that they are working on it, but don't have any answer yet.... I guess the issue rises when you duplicate your module. So, in my testbench, I am instantiated my unit under test (uut) four times, and it seems that it is related to the issue that I am seeing. 

 

--Rudy 

1,365 Views
Registered: ‎01-22-2015

Re: RTL error or possible issue with Vivado 2017.3 ?

@rudy Thanks for the update!  

I hope you’ll tell us if/how the problem is solved.

 

mark

0 Kudos
Explorer
Explorer
1,295 Views
Registered: ‎09-07-2011

Re: RTL error or possible issue with Vivado 2017.3 ?

@rudy , are uut_1, uut_2, uut_4, and uut_8 all instances of the same block?

0 Kudos
1,279 Views
Registered: ‎01-22-2015

Re: RTL error or possible issue with Vivado 2017.3 ?

@rudy  Did you define your custom signal type, input_array_t, in a VHDL package file?  -and are you using input_array_t to define inputs/outputs of the VHDL component that describes each uut?

 

Remember, I'm pulling for ya.  We're all in this together!    -Red Green

0 Kudos