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Visitor ender.culha
Visitor
7,946 Views
Registered: ‎12-24-2010

RTL synthesis problem

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Hello, for my master thesis  am studying on a software which creates and connects arithmetic components in vhdl. In my thesis reports, i need to show these outputs as graphics but RTL synthesis shows wrong circuit. For example, I connected 3 adders with every input and output to the module is registered. The VHDL code is below; But the RTL schematic is shown in the figure. d_3 is registered but the output of register seems to going anywhere. But in fact it isi going RCAAdder_212_101. It is correct when i simulated behaviorally but RTL schematic seems wrong.What can i do? Is there any other way to show RTL schematic correct.RTL.png

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.VComponents.all;
entity Example2  is
port (
	d_0: in std_logic_vector(0 downto 0);
	d_1: in std_logic_vector(1 downto 0);
	d_2: in std_logic_vector(3 downto 0);
	d_3: in std_logic_vector(2 downto 0);
	clk: in  std_logic;
	out_d_0: out std_logic_vector(5 downto 0));
end entity;
architecture Structural of Example2 is
	component RCAAdder_212_100_i1_2_i2_2 is
			generic (g_BITSIZE: integer := 2);
			port (d_0 : in std_logic_vector(g_BITSIZE-1 downto 0);
			d_1 : in std_logic_vector(g_BITSIZE-1 downto 0);
			out_d_0 : out std_logic_vector(g_BITSIZE downto 0));
end component;
	component RCAAdder_212_101_i1_4_i2_4 is
			generic (g_BITSIZE: integer := 4);
			port (d_0 : in std_logic_vector(g_BITSIZE-1 downto 0);
			d_1 : in std_logic_vector(g_BITSIZE-1 downto 0);
			out_d_0 : out std_logic_vector(g_BITSIZE downto 0));
end component;
	component RCAAdder_212_102_i1_5_i2_5 is
			generic (g_BITSIZE: integer := 5);
			port (d_0 : in std_logic_vector(g_BITSIZE-1 downto 0);
			d_1 : in std_logic_vector(g_BITSIZE-1 downto 0);
			out_d_0 : out std_logic_vector(g_BITSIZE downto 0));
end component;
	signal  d_0_r0 : std_logic_vector(0 downto 0);
	signal  d_1_r0 : std_logic_vector(1 downto 0);
	signal  d_2_r0 : std_logic_vector(3 downto 0);
	signal  d_3_r0 : std_logic_vector(2 downto 0);
	signal  RCAAdder0_d0 : std_logic_vector(2 downto 0);
	signal  RCAAdder1_d0 : std_logic_vector(4 downto 0);
	signal  RCAAdder2_d0 : std_logic_vector(5 downto 0);
	signal d_0_r0_e : std_logic_vector( 1 downto 0);
	signal d_3_r0_e : std_logic_vector( 3 downto 0);
	signal RCAAdder0_d0_e : std_logic_vector( 4 downto 0);
	begin
	reg_inst0 : process(clk)
	begin
		if (clk'event and clk='1') then
		d_0_r0 <= d_0;
	end if;
	end process;
	reg_inst1 : process(clk)
	begin
		if (clk'event and clk='1') then
		d_1_r0 <= d_1;
	end if;
	end process;
	reg_inst2 : process(clk)
	begin
		if (clk'event and clk='1') then
		d_2_r0 <= d_2;
	end if;
	end process;
	reg_inst3 : process(clk)
	begin
		if (clk'event and clk='1') then
		d_3_r0 <= d_3;
	end if;
	end process;
	d_0_r0_e <= d_0_r0 & "0";
	d_3_r0_e <= d_3_r0 & "0";
	RCAAdder0_d0_e <= RCAAdder0_d0 & "00";
	inst_0_RCAAdder_0 : RCAAdder_212_100_i1_2_i2_2 port map (d_0 => d_0_r0_e , d_1 => d_1_r0 , out_d_0 => RCAAdder0_d0);
	inst_1_RCAAdder_1 : RCAAdder_212_101_i1_4_i2_4 port map (d_0 => d_2_r0 , d_1 => d_3_r0_e , out_d_0 => RCAAdder1_d0);
	inst_2_RCAAdder_2 : RCAAdder_212_102_i1_5_i2_5 port map (d_0 => RCAAdder0_d0_e , d_1 => RCAAdder1_d0 , out_d_0 => RCAAdder2_d0);
	reg_int4 : process(clk)
	begin
		if (clk'event and clk='1') then
		out_d_0 <= RCAAdder2_d0;
	end if;
	end process;
end Architecture;

 

 

 

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RTL.png
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Visitor ender.culha
Visitor
10,317 Views
Registered: ‎12-24-2010

Re: RTL synthesis problem

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Thank you. But I don't need  synthesized netlist and FPGA resources because it is so complicated to trace and show in master thesis, RTL schematic is exactly what i want because i can see my arithmetic component and how they are connected. 

I synthesized this circuit with different versions of Xilinx ISE.(Above RTL schematic is for 12.4). I tried it with 13.1 and 13.2, it was the same of 12.4. I also synthesized it ISE 8.2 and here the RTL schematic was correct.(schematic below)RTL8_2.png Why? What is the problem with newer versions?

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Advisor eilert
Advisor
7,935 Views
Registered: ‎08-14-2007

Re: RTL synthesis problem

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Hi,

the RTL-Viewer is known for its inaccurate results.

 

There's hardly anything you can do about it with ISE.

But maybe someone at your faculty has access to Mentor Precision RTL.

(Or you ask for a eval license).

 

This program can be intgrated into ISE as a 3rd-Party tool and provides a much better output of the synthesis results.

 

Have a nice synthesis

  Eilert

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Visitor ender.culha
Visitor
7,924 Views
Registered: ‎12-24-2010

Re: RTL synthesis problem

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Thanks, is there any other way to show synthesized blocks in xilinx ise? It is not easy to find license for mentor.

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Xilinx Employee
Xilinx Employee
7,913 Views
Registered: ‎11-28-2007

Re: RTL synthesis problem

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Yes, you can use PlanAhead to look at the synthesized netlist (see the snapshot below).

 

ScreenHunter_16.jpg


@ender.culha wrote:

Thanks, is there any other way to show synthesized blocks in xilinx ise? It is not easy to find license for mentor.




Cheers,
Jim
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Visitor ender.culha
Visitor
10,318 Views
Registered: ‎12-24-2010

Re: RTL synthesis problem

Jump to solution

Thank you. But I don't need  synthesized netlist and FPGA resources because it is so complicated to trace and show in master thesis, RTL schematic is exactly what i want because i can see my arithmetic component and how they are connected. 

I synthesized this circuit with different versions of Xilinx ISE.(Above RTL schematic is for 12.4). I tried it with 13.1 and 13.2, it was the same of 12.4. I also synthesized it ISE 8.2 and here the RTL schematic was correct.(schematic below)RTL8_2.png Why? What is the problem with newer versions?

View solution in original post

0 Kudos