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Registered: ‎04-02-2018

Re: Project with PmodCLP module cannot synthesize --INTERNAL_ERROR:Xst:cmain.c:3423:1.29

28/5000
Can you tell me how to solve this problem,?I have the same problem, thank you!

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Registered: ‎07-21-2014

Re: Project with PmodCLP module cannot synthesize --INTERNAL_ERROR:Xst:cmain.c:3423:1.29

@mr_zhang

 

Looks like XST crash issue. Can you please share the complete log file?

 

Thanks

Anusheel

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Re: Project with PmodCLP module cannot synthesize --INTERNAL_ERROR:Xst:cmain.c:3423:1.29

210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 160: Output port <de_o> of the instance <YUV422_2YUV444_u1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 160: Output port <hs_o> of the instance <YUV422_2YUV444_u1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 160: Output port <vs_o> of the instance <YUV422_2YUV444_u1> is unconnected or connected to loadless signal.
Found 1-bit register for signal <vs_d0>.
Found 1-bit register for signal <vs_d1>.
Found 1-bit register for signal <frame_flag>.
Found 1-bit register for signal <pixel_rd_req_d0>.
Found 9-bit comparator greater for signal <scaler_fifo_afull> created at line 120
Summary:
inferred 4 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <vout_pro_1> synthesized.

Synthesizing Unit <vout_frame_buffer_ctrl_1>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v".
MEM_DATA_BITS = 64
WITDH_2K = 1
WARNING:Xst:647 - Input <vout_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wr_max_line> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 70: Output port <rd_data_count> of the instance <vout_frame_buffer_ctrlfifo_256_64i_16o_m0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 70: Output port <full> of the instance <vout_frame_buffer_ctrlfifo_256_64i_16o_m0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 103: Output port <rdusedw> of the instance <vout_frame_buffer_ctrl_fifo_256_16_m1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 103: Output port <wrfull> of the instance <vout_frame_buffer_ctrl_fifo_256_16_m1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 103: Output port <rdvalid> of the instance <vout_frame_buffer_ctrl_fifo_256_16_m1> is unconnected or connected to loadless signal.
Found 1-bit register for signal <mem_rd_buf_wren>.
Found 10-bit register for signal <byte_per_line>.
Found 10-bit register for signal <byte_per_line_at_vout_clk>.
Found 10-bit register for signal <remain_len>.
Found 10-bit register for signal <rd_burst_len>.
Found 24-bit register for signal <rd_burst_addr>.
Found 12-bit register for signal <rd_cnt>.
Found 12-bit register for signal <wait_time>.
Found 12-bit register for signal <burst_line>.
Found 3-bit register for signal <burst_state>.
Found 2-bit register for signal <rd_frame_addr>.
Found 1-bit register for signal <data_dirty>.
Found 1-bit register for signal <rd_burst_req>.
Found 1-bit register for signal <data_fifo_full>.
Found 1-bit register for signal <data_fifo_full_d0>.
Found 1-bit register for signal <vout_vs_d0>.
Found 1-bit register for signal <vout_vs_d1>.
Found 1-bit register for signal <frame_flag_at_vout_clk>.
Found 1-bit register for signal <data_dirty_flag>.
Found 1-bit register for signal <vout_vs_mem_clk_d0>.
Found 1-bit register for signal <vout_vs_mem_clk_d1>.
Found 1-bit register for signal <frame_flag>.
Found 1-bit register for signal <mem_buf_rd_req_d0>.
Found finite state machine <FSM_1> for signal <burst_state>.
-----------------------------------------------------------------------
| States | 6 |
| Transitions | 17 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | mem_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 000 |
| Power Up State | 000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 12-bit subtractor for signal <vout_width_rec_at_vout_clk[11]_GND_39_o_sub_15_OUT> created at line 164.
Found 12-bit subtractor for signal <vout_width[11]_GND_39_o_sub_17_OUT> created at line 166.
Found 2-bit subtractor for signal <wr_frame_addr[1]_GND_39_o_sub_61_OUT> created at line 304.
Found 10-bit subtractor for signal <remain_len[9]_GND_39_o_sub_68_OUT> created at line 320.
Found 10-bit adder for signal <vout_width[11]_GND_39_o_add_5_OUT> created at line 138.
Found 24-bit adder for signal <rd_burst_addr[23]_GND_39_o_add_22_OUT> created at line 187.
Found 12-bit adder for signal <rd_cnt[11]_GND_39_o_add_30_OUT> created at line 208.
Found 12-bit adder for signal <wait_time[11]_GND_39_o_add_40_OUT> created at line 247.
Found 12-bit adder for signal <burst_line[11]_GND_39_o_add_56_OUT> created at line 294.
Found 3-bit 7-to-1 multiplexer for signal <burst_state_next> created at line 255.
Found 9-bit comparator greater for signal <GND_39_o_fif0_8_16_wrusedw[8]_LessThan_3_o> created at line 119
Found 12-bit comparator equal for signal <rd_cnt[11]_vout_width_rec_at_vout_clk[11]_equal_16_o> created at line 164
Found 12-bit comparator not equal for signal <rd_cnt[11]_vout_width[11]_equal_18_o> created at line 166
Found 12-bit comparator greater for signal <GND_39_o_wait_time[11]_LessThan_45_o> created at line 257
Found 8-bit comparator greater for signal <wrusedw[7]_GND_39_o_LessThan_51_o> created at line 276
Found 10-bit comparator greater for signal <remain_len[9]_GND_39_o_LessThan_67_o> created at line 317
Found 10-bit comparator greater for signal <GND_39_o_remain_len[9]_LessThan_75_o> created at line 331
Summary:
inferred 9 Adder/Subtractor(s).
inferred 115 D-type flip-flop(s).
inferred 7 Comparator(s).
inferred 13 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <vout_frame_buffer_ctrl_1> synthesized.

Synthesizing Unit <lite_fifo_3>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\lite_fifo.v".
COMMON_CLOCK = 1
ADDR_WIDTH = 8
DATA_WIDTH = 16
USE_RAM_OUTPUT_REGISTER = 0
Found 1-bit register for signal <rdvalid>.
Found 1-bit register for signal <wrfull>.
Found 9-bit register for signal <wrptr_b_rd>.
Found 9-bit register for signal <rdusedw>.
Found 9-bit register for signal <wrptr_b_wr>.
Found 9-bit register for signal <wrusedw>.
Found 9-bit register for signal <rdptr_b_rd>.
Found 1-bit register for signal <ra_held>.
Found 1-bit register for signal <rdempty>.
Found 16-bit register for signal <q_reg>.
Found 9-bit subtractor for signal <wrptr_b_rd[8]_rdptr_b_rd_next[8]_sub_8_OUT> created at line 150.
Found 9-bit subtractor for signal <wrptr_b_wr_next[8]_rdptr_b_rd[8]_sub_22_OUT> created at line 225.
Found 9-bit adder for signal <rdptr_b_rd[8]_GND_41_o_add_3_OUT> created at line 86.
Found 9-bit adder for signal <wrptr_b_wr[8]_GND_41_o_add_19_OUT> created at line 188.
Found 9-bit comparator not equal for signal <n0001> created at line 83
Found 9-bit comparator equal for signal <wrptr_b_rd[8]_rdptr_b_rd_next[8]_equal_10_o> created at line 151
Found 8-bit comparator not equal for signal <n0019> created at line 184
Found 1-bit comparator equal for signal <rdptr_b_rd[8]_wrptr_b_wr[8]_equal_19_o> created at line 185
Found 8-bit comparator equal for signal <rdptr_b_rd[7]_wrptr_b_wr_next[7]_equal_23_o> created at line 227
Found 1-bit comparator not equal for signal <n0028> created at line 228
Summary:
inferred 4 Adder/Subtractor(s).
inferred 65 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 4 Multiplexer(s).
Unit <lite_fifo_3> synthesized.

Synthesizing Unit <dp_ram_3>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\dp_ram.v".
DATA_WIDTH = 16
MEM_SIZE = 256
Set property "syn_ramstyle = block_ram" for signal <mem>.
Found 256x16-bit dual-port RAM <Mram_mem> for signal <mem>.
Found 8-bit register for signal <read_addr>.
Summary:
inferred 1 RAM(s).
inferred 8 D-type flip-flop(s).
Unit <dp_ram_3> synthesized.

Synthesizing Unit <scaler_1>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v".
WITDH_2K = 1
WARNING:Xst:2898 - Port 'a_coff_next', unconnected in block instance 'calu_H', is tied to GND.
WARNING:Xst:2898 - Port 'b_coff_next', unconnected in block instance 'calu_H', is tied to GND.
WARNING:Xst:2898 - Port 'data_en_in', unconnected in block instance 'calu_H', is tied to GND.
WARNING:Xst:2898 - Port 'i_hs', unconnected in block instance 'yuv444_yuv422_m0', is tied to GND.
WARNING:Xst:647 - Input <s_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <t_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v" line 758: Output port <a_coff_next_out> of the instance <calu_H> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v" line 758: Output port <b_coff_next_out> of the instance <calu_H> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v" line 758: Output port <data_en_out> of the instance <calu_H> is unconnected or connected to loadless signal.
Found 4-bit register for signal <wr_state>.
Found 4-bit register for signal <scale_state>.
Found 4-bit register for signal <rd_pixel_state>.
Found 4-bit register for signal <col_calu_state>.
Found 12-bit register for signal <wr_cnt>.
Found 12-bit register for signal <rd_req_cnt>.
Found 12-bit register for signal <wr_lines>.
Found 12-bit register for signal <rd_col>.
Found 12-bit register for signal <scale_col>.
Found 20-bit register for signal <scale_map_line>.
Found 20-bit register for signal <map_col>.
Found 9-bit register for signal <h_coff_sum>.
Found 1-bit register for signal <rd_req_en>.
Found 1-bit register for signal <wr_buf_sel>.
Found 1-bit register for signal <one_line_req_end_d0>.
Found 1-bit register for signal <one_line_req_end_d1>.
Found 1-bit register for signal <one_line_req_end_d2>.
Found 1-bit register for signal <one_line_req_end_d3>.
Found 1-bit register for signal <one_line_req_end_d4>.
Found 1-bit register for signal <rd_buf_req_d0>.
Found 1-bit register for signal <rd_buf_req_d1>.
Found 1-bit register for signal <col_calu_state_idle_d0>.
Found 16-bit register for signal <K_h_reg>.
Found 16-bit register for signal <K_v_reg>.
Found 1-bit register for signal <H_scale_down>.
Found 1-bit register for signal <H_scale_up>.
Found 1-bit register for signal <pixel_data_read_en>.
Found 1-bit register for signal <pixel_data_read_en_d0>.
Found 8-bit register for signal <a_coff_V>.
Found 8-bit register for signal <b_coff_V>.
Found 24-bit register for signal <line0_pixel_data>.
Found 24-bit register for signal <line1_pixel_data>.
Found 1-bit register for signal <scale_data_out_V_d0>.
Found 24-bit register for signal <pixel_data0>.
Found 24-bit register for signal <pixel_data1>.
Found 8-bit register for signal <a_coff_H_from_V_d0>.
Found 8-bit register for signal <b_coff_H_from_V_d0>.
Found 1-bit register for signal <scale_data_en>.
Found 1-bit register for signal <scale_data_en_d0>.
Found 8-bit register for signal <a_coff_H>.
Found 8-bit register for signal <b_coff_H>.
Found 8-bit register for signal <a_coff_H_d0>.
Found 8-bit register for signal <b_coff_H_d0>.
Found 12-bit register for signal <pix_cnt>.
Found 1-bit register for signal <rd_req_d0>.
Found finite state machine <FSM_2> for signal <wr_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 16 |
| Inputs | 6 |
| Outputs | 5 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
INFO:Xst:1799 - State 0100 is never reached in FSM <scale_state>.
Found finite state machine <FSM_3> for signal <scale_state>.
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 13 |
| Inputs | 6 |
| Outputs | 6 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_4> for signal <rd_pixel_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 21 |
| Inputs | 8 |
| Outputs | 4 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_5> for signal <col_calu_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 17 |
| Inputs | 7 |
| Outputs | 3 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 12-bit subtractor for signal <wr_lines[11]_GND_44_o_sub_6_OUT> created at line 127.
Found 12-bit subtractor for signal <s_width[11]_GND_44_o_sub_9_OUT> created at line 130.
Found 9-bit adder for signal <n0327> created at line 123.
Found 20-bit adder for signal <map_col_next> created at line 136.
Found 12-bit adder for signal <wr_cnt[11]_GND_44_o_add_37_OUT> created at line 279.
Found 12-bit adder for signal <rd_req_cnt[11]_GND_44_o_add_43_OUT> created at line 299.
Found 12-bit adder for signal <wr_lines[11]_GND_44_o_add_48_OUT> created at line 319.
Found 20-bit adder for signal <scale_map_line[19]_GND_44_o_add_70_OUT> created at line 398.
Found 12-bit adder for signal <rd_col[11]_GND_44_o_add_95_OUT> created at line 483.
Found 12-bit adder for signal <rd_col[11]_GND_44_o_add_117_OUT> created at line 562.
Found 12-bit adder for signal <map_col[19]_GND_44_o_add_127_OUT> created at line 603.
Found 12-bit adder for signal <map_col_next[19]_GND_44_o_add_131_OUT> created at line 618.
Found 12-bit adder for signal <scale_col[11]_GND_44_o_add_150_OUT> created at line 649.
Found 12-bit adder for signal <pix_cnt[11]_GND_44_o_add_192_OUT> created at line 774.
Found 4-bit 4-to-1 multiplexer for signal <wr_state_next> created at line 34.
Found 4-bit 4-to-1 multiplexer for signal <rd_pixel_state_next> created at line 71.
Found 12-bit comparator equal for signal <line_data_is_ready> created at line 127
Found 12-bit comparator equal for signal <rd_req_cnt[11]_s_width[11]_equal_10_o> created at line 130
Found 12-bit comparator equal for signal <rd_col[11]_s_width[11]_equal_15_o> created at line 135
Found 12-bit comparator greater for signal <rd_col[11]_GND_44_o_LessThan_97_o> created at line 483
Found 12-bit comparator equal for signal <rd_col[11]_map_col[19]_equal_129_o> created at line 603
Found 12-bit comparator equal for signal <rd_col[11]_map_col_next[19]_equal_133_o> created at line 618
Found 12-bit comparator equal for signal <rd_col[11]_map_col_next[19]_equal_137_o> created at line 619
Summary:
inferred 14 Adder/Subtractor(s).
inferred 331 D-type flip-flop(s).
inferred 7 Comparator(s).
inferred 14 Multiplexer(s).
inferred 4 Finite State Machine(s).
Unit <scaler_1> synthesized.

Synthesizing Unit <line_buf_scaler_1>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\line_buf_scaler.v".
WITDH_2K = 1
Summary:
no macro.
Unit <line_buf_scaler_1> synthesized.

Synthesizing Unit <dp_ram_4>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\dp_ram.v".
DATA_WIDTH = 8
MEM_SIZE = 2048
Set property "syn_ramstyle = block_ram" for signal <mem>.
Found 2048x8-bit dual-port RAM <Mram_mem> for signal <mem>.
Found 11-bit register for signal <read_addr>.
Summary:
inferred 1 RAM(s).
inferred 11 D-type flip-flop(s).
Unit <dp_ram_4> synthesized.

Synthesizing Unit <dp_ram_5>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\dp_ram.v".
DATA_WIDTH = 8
MEM_SIZE = 1024
Set property "syn_ramstyle = block_ram" for signal <mem>.
Found 1024x8-bit dual-port RAM <Mram_mem> for signal <mem>.
Found 10-bit register for signal <read_addr>.
Summary:
inferred 1 RAM(s).
inferred 10 D-type flip-flop(s).
Unit <dp_ram_5> synthesized.

Synthesizing Unit <calu>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\calu.v".
Found 24-bit register for signal <b_reg>.
Found 8-bit register for signal <a_coff_reg>.
Found 8-bit register for signal <b_coff_reg>.
Found 1-bit register for signal <data_en_in_d0>.
Found 1-bit register for signal <scale_en_in_d0>.
Found 8-bit register for signal <a_coff_next_d0>.
Found 8-bit register for signal <b_coff_next_d0>.
Found 16-bit register for signal <a_mult0>.
Found 16-bit register for signal <a_mult1>.
Found 16-bit register for signal <a_mult2>.
Found 16-bit register for signal <b_mult0>.
Found 16-bit register for signal <b_mult1>.
Found 16-bit register for signal <b_mult2>.
Found 1-bit register for signal <data_en_in_d1>.
Found 1-bit register for signal <scale_en_in_d1>.
Found 8-bit register for signal <a_coff_next_d1>.
Found 8-bit register for signal <b_coff_next_d1>.
Found 16-bit register for signal <add0>.
Found 16-bit register for signal <add1>.
Found 16-bit register for signal <add2>.
Found 1-bit register for signal <data_en_in_d2>.
Found 1-bit register for signal <scale_en_in_d2>.
Found 8-bit register for signal <a_coff_next_d2>.
Found 8-bit register for signal <b_coff_next_d2>.
Found 9-bit register for signal <add_tmp0>.
Found 9-bit register for signal <add_tmp1>.
Found 9-bit register for signal <add_tmp2>.
Found 1-bit register for signal <data_en_out>.
Found 1-bit register for signal <scale_en_out>.
Found 8-bit register for signal <a_coff_next_out>.
Found 8-bit register for signal <b_coff_next_out>.
Found 24-bit register for signal <a_reg>.
Found 16-bit adder for signal <a_mult0[15]_b_mult0[15]_add_23_OUT> created at line 91.
Found 16-bit adder for signal <a_mult1[15]_b_mult1[15]_add_24_OUT> created at line 92.
Found 16-bit adder for signal <a_mult2[15]_b_mult2[15]_add_25_OUT> created at line 93.
Found 9-bit adder for signal <n0095> created at line 102.
Found 9-bit adder for signal <n0099> created at line 103.
Found 9-bit adder for signal <n0100> created at line 104.
Found 8x8-bit multiplier for signal <a_reg[7]_a_coff_reg[7]_MuLt_8_OUT> created at line 76.
Found 8x8-bit multiplier for signal <a_reg[15]_a_coff_reg[7]_MuLt_9_OUT> created at line 77.
Found 8x8-bit multiplier for signal <a_reg[23]_a_coff_reg[7]_MuLt_10_OUT> created at line 78.
Found 8x8-bit multiplier for signal <b_reg[7]_b_coff_reg[7]_MuLt_11_OUT> created at line 80.
Found 8x8-bit multiplier for signal <b_reg[15]_b_coff_reg[7]_MuLt_12_OUT> created at line 81.
Found 8x8-bit multiplier for signal <b_reg[23]_b_coff_reg[7]_MuLt_13_OUT> created at line 82.
Found 8-bit comparator greater for signal <GND_48_o_add0[7]_LessThan_33_o> created at line 102
Found 8-bit comparator greater for signal <GND_48_o_add1[7]_LessThan_35_o> created at line 103
Found 8-bit comparator greater for signal <GND_48_o_add2[7]_LessThan_37_o> created at line 104
Summary:
inferred 6 Multiplier(s).
inferred 6 Adder/Subtractor(s).
inferred 307 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 3 Multiplexer(s).
Unit <calu> synthesized.

Synthesizing Unit <YUV422_2YUV444>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\YUV422_2YUV444.v".
Found 1-bit register for signal <hs_o>.
Found 1-bit register for signal <vs_o>.
Found 1-bit register for signal <flag>.
Found 8-bit register for signal <y_o>.
Found 8-bit register for signal <cb>.
Found 8-bit register for signal <cr>.
Found 1-bit register for signal <de_o>.
Summary:
inferred 28 D-type flip-flop(s).
Unit <YUV422_2YUV444> synthesized.

Synthesizing Unit <video_pro_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\video_pro.v".
MEM_DATA_BITS = 64
INTERLACE = 1
WARNING:Xst:2898 - Port 'wr_max_line', unconnected in block instance 'vout_pro_m0', is tied to GND.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\video_pro.v" line 58: Output port <wr_max_line> of the instance <vin_pro_m0> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <video_pro_2> synthesized.

Synthesizing Unit <vin_pro_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_pro.v".
MEM_DATA_BITS = 64
INTERLACE = 1
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_pro.v" line 132: Output port <rdusedw> of the instance <buffer_f> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_pro.v" line 132: Output port <wrusedw> of the instance <buffer_f> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_pro.v" line 132: Output port <wrfull> of the instance <buffer_f> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_pro.v" line 132: Output port <rdvalid> of the instance <buffer_f> is unconnected or connected to loadless signal.
Found 1-bit register for signal <vs_d1>.
Found 1-bit register for signal <frame_flag>.
Found 1-bit register for signal <vs_vclk_d0>.
Found 1-bit register for signal <vs_vclk_d1>.
Found 12-bit register for signal <vin_x_cnt>.
Found 12-bit register for signal <vin_y_cnt>.
Found 1-bit register for signal <clipper_wr_en0>.
Found 1-bit register for signal <clipper_wr_en1>.
Found 1-bit register for signal <buffer_f_wrreq>.
Found 16-bit register for signal <buffer_f_data>.
Found 1-bit register for signal <vfb_vin_de>.
Found 1-bit register for signal <vs_d0>.
Found 12-bit adder for signal <vin_x_cnt[11]_GND_51_o_add_4_OUT> created at line 66.
Found 12-bit adder for signal <vin_y_cnt[11]_GND_51_o_add_12_OUT> created at line 80.
Found 12-bit comparator greater for signal <clipper_left[11]_vin_x_cnt[11]_LessThan_20_o> created at line 90
Found 12-bit comparator lessequal for signal <n0024> created at line 90
Found 12-bit comparator greater for signal <clipper_top[11]_vin_y_cnt[11]_LessThan_24_o> created at line 97
Found 12-bit comparator lessequal for signal <n0030> created at line 97
Summary:
inferred 2 Adder/Subtractor(s).
inferred 49 D-type flip-flop(s).
inferred 4 Comparator(s).
inferred 2 Multiplexer(s).
Unit <vin_pro_2> synthesized.

Synthesizing Unit <vin_frame_buffer_ctrl_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_frame_buffer_ctrl.v".
MEM_DATA_BITS = 64
INTERLACE = 1
WARNING:Xst:647 - Input <vin_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_frame_buffer_ctrl.v" line 84: Output port <rdempty> of the instance <vin_frame_buffer_ctrl_fifo_m0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_frame_buffer_ctrl.v" line 84: Output port <wrfull> of the instance <vin_frame_buffer_ctrl_fifo_m0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vin_frame_buffer_ctrl.v" line 84: Output port <rdvalid> of the instance <vin_frame_buffer_ctrl_fifo_m0> is unconnected or connected to loadless signal.
Found 10-bit register for signal <byte_per_line>.
Found 10-bit register for signal <remain_len>.
Found 10-bit register for signal <wr_burst_len>.
Found 24-bit register for signal <wr_burst_addr>.
Found 3-bit register for signal <burst_state>.
Found 12-bit register for signal <wr_max_line>.
Found 12-bit register for signal <burst_line>.
Found 2-bit register for signal <frame_addr>.
Found 1-bit register for signal <wr_burst_req>.
Found 1-bit register for signal <vin_vs_d0>.
Found 1-bit register for signal <vin_vs_d1>.
Found 1-bit register for signal <frame_flag_vin>.
Found 12-bit register for signal <data_cnt>.
Found 16-bit register for signal <pixel0>.
Found 16-bit register for signal <pixel1>.
Found 16-bit register for signal <pixel2>.
Found 16-bit register for signal <pixel3>.
Found 1-bit register for signal <fifo_wr_req>.
Found 1-bit register for signal <vin_vs_mem_clk_d0>.
Found 1-bit register for signal <vin_vs_mem_clk_d1>.
Found 1-bit register for signal <frame_flag>.
Found 1-bit register for signal <fifo_afull>.
Found finite state machine <FSM_6> for signal <burst_state>.
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 13 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | mem_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 000 |
| Power Up State | 000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 10-bit subtractor for signal <remain_len[9]_GND_52_o_sub_56_OUT> created at line 227.
Found 10-bit subtractor for signal <remain_len[9]_GND_52_o_sub_75_OUT> created at line 282.
Found 12-bit adder for signal <data_cnt[11]_GND_52_o_add_7_OUT> created at line 115.
Found 24-bit adder for signal <wr_burst_addr[23]_GND_52_o_add_42_OUT> created at line 188.
Found 12-bit adder for signal <burst_line[11]_GND_52_o_add_63_OUT> created at line 255.
Found 2-bit adder for signal <frame_addr[1]_GND_52_o_add_67_OUT> created at line 265.
Found 8-bit comparator greater for signal <PWR_48_o_wrusedw[7]_LessThan_2_o> created at line 66
Found 8-bit comparator greater for signal <GND_52_o_rdusedw[7]_LessThan_50_o> created at line 213
Found 8-bit comparator lessequal for signal <n0061> created at line 227
Found 10-bit comparator greater for signal <n0063> created at line 227
Found 10-bit comparator lessequal for signal <n0066> created at line 227
Found 10-bit comparator greater for signal <remain_len[9]_GND_52_o_LessThan_74_o> created at line 279
Summary:
inferred 6 Adder/Subtractor(s).
inferred 165 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 7 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <vin_frame_buffer_ctrl_2> synthesized.

Synthesizing Unit <vout_pro_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v".
MEM_DATA_BITS = 64
WITDH_2K = 0
WARNING:Xst:2898 - Port 'hs_i', unconnected in block instance 'YUV422_2YUV444_u1', is tied to GND.
WARNING:Xst:2898 - Port 'vs_i', unconnected in block instance 'YUV422_2YUV444_u1', is tied to GND.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 133: Output port <rdusedw> of the instance <out_buff0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 133: Output port <rdempty> of the instance <out_buff0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 133: Output port <wrfull> of the instance <out_buff0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 133: Output port <rdvalid> of the instance <out_buff0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 160: Output port <de_o> of the instance <YUV422_2YUV444_u1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 160: Output port <hs_o> of the instance <YUV422_2YUV444_u1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_pro.v" line 160: Output port <vs_o> of the instance <YUV422_2YUV444_u1> is unconnected or connected to loadless signal.
Found 1-bit register for signal <vs_d0>.
Found 1-bit register for signal <vs_d1>.
Found 1-bit register for signal <frame_flag>.
Found 1-bit register for signal <pixel_rd_req_d0>.
Found 9-bit comparator greater for signal <scaler_fifo_afull> created at line 120
Summary:
inferred 4 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <vout_pro_2> synthesized.

Synthesizing Unit <vout_frame_buffer_ctrl_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v".
MEM_DATA_BITS = 64
WITDH_2K = 0
WARNING:Xst:647 - Input <vout_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wr_max_line> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 70: Output port <rd_data_count> of the instance <vout_frame_buffer_ctrlfifo_256_64i_16o_m0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 70: Output port <full> of the instance <vout_frame_buffer_ctrlfifo_256_64i_16o_m0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 103: Output port <rdusedw> of the instance <vout_frame_buffer_ctrl_fifo_256_16_m1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 103: Output port <wrfull> of the instance <vout_frame_buffer_ctrl_fifo_256_16_m1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\vout_frame_buffer_ctrl.v" line 103: Output port <rdvalid> of the instance <vout_frame_buffer_ctrl_fifo_256_16_m1> is unconnected or connected to loadless signal.
Found 1-bit register for signal <mem_rd_buf_wren>.
Found 10-bit register for signal <byte_per_line>.
Found 10-bit register for signal <remain_len>.
Found 10-bit register for signal <rd_burst_len>.
Found 24-bit register for signal <rd_burst_addr>.
Found 12-bit register for signal <wait_time>.
Found 12-bit register for signal <burst_line>.
Found 3-bit register for signal <burst_state>.
Found 2-bit register for signal <rd_frame_addr>.
Found 1-bit register for signal <rd_burst_req>.
Found 1-bit register for signal <data_fifo_full>.
Found 1-bit register for signal <data_fifo_full_d0>.
Found 1-bit register for signal <vout_vs_mem_clk_d0>.
Found 1-bit register for signal <vout_vs_mem_clk_d1>.
Found 1-bit register for signal <frame_flag>.
Found 1-bit register for signal <mem_buf_rd_req_d0>.
Found finite state machine <FSM_7> for signal <burst_state>.
-----------------------------------------------------------------------
| States | 6 |
| Transitions | 17 |
| Inputs | 5 |
| Outputs | 7 |
| Clock | mem_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 000 |
| Power Up State | 000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 2-bit subtractor for signal <wr_frame_addr[1]_GND_54_o_sub_61_OUT> created at line 304.
Found 10-bit subtractor for signal <remain_len[9]_GND_54_o_sub_68_OUT> created at line 320.
Found 24-bit adder for signal <rd_burst_addr[23]_GND_54_o_add_22_OUT> created at line 187.
Found 12-bit adder for signal <wait_time[11]_GND_54_o_add_40_OUT> created at line 247.
Found 12-bit adder for signal <burst_line[11]_GND_54_o_add_56_OUT> created at line 294.
Found 3-bit 7-to-1 multiplexer for signal <burst_state_next> created at line 255.
Found 9-bit comparator greater for signal <GND_54_o_fif0_8_16_wrusedw[8]_LessThan_3_o> created at line 119
Found 12-bit comparator greater for signal <GND_54_o_wait_time[11]_LessThan_45_o> created at line 257
Found 8-bit comparator greater for signal <wrusedw[7]_GND_54_o_LessThan_51_o> created at line 276
Found 10-bit comparator greater for signal <remain_len[9]_GND_54_o_LessThan_67_o> created at line 317
Found 10-bit comparator greater for signal <GND_54_o_remain_len[9]_LessThan_75_o> created at line 331
WARNING:Xst:2404 - FFs/Latches <data_dirty_flag<0:0>> (without init value) have a constant value of 0 in block <vout_frame_buffer_ctrl_2>.
WARNING:Xst:2404 - FFs/Latches <data_dirty<0:0>> (without init value) have a constant value of 0 in block <vout_frame_buffer_ctrl_2>.
Summary:
inferred 5 Adder/Subtractor(s).
inferred 88 D-type flip-flop(s).
inferred 5 Comparator(s).
inferred 9 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <vout_frame_buffer_ctrl_2> synthesized.

Synthesizing Unit <scaler_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v".
WITDH_2K = 0
WARNING:Xst:2898 - Port 'a_coff_next', unconnected in block instance 'calu_H', is tied to GND.
WARNING:Xst:2898 - Port 'b_coff_next', unconnected in block instance 'calu_H', is tied to GND.
WARNING:Xst:2898 - Port 'data_en_in', unconnected in block instance 'calu_H', is tied to GND.
WARNING:Xst:2898 - Port 'i_hs', unconnected in block instance 'yuv444_yuv422_m0', is tied to GND.
WARNING:Xst:647 - Input <s_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <t_height> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v" line 758: Output port <a_coff_next_out> of the instance <calu_H> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v" line 758: Output port <b_coff_next_out> of the instance <calu_H> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Think\Desktop\3.23\src\common_rtl\video\scaler.v" line 758: Output port <data_en_out> of the instance <calu_H> is unconnected or connected to loadless signal.
Found 4-bit register for signal <wr_state>.
Found 4-bit register for signal <scale_state>.
Found 4-bit register for signal <rd_pixel_state>.
Found 4-bit register for signal <col_calu_state>.
Found 12-bit register for signal <wr_cnt>.
Found 12-bit register for signal <rd_req_cnt>.
Found 12-bit register for signal <wr_lines>.
Found 12-bit register for signal <rd_col>.
Found 12-bit register for signal <scale_col>.
Found 20-bit register for signal <scale_map_line>.
Found 20-bit register for signal <map_col>.
Found 1-bit register for signal <rd_req_en>.
Found 1-bit register for signal <wr_buf_sel>.
Found 1-bit register for signal <one_line_req_end_d0>.
Found 1-bit register for signal <one_line_req_end_d1>.
Found 1-bit register for signal <one_line_req_end_d2>.
Found 1-bit register for signal <one_line_req_end_d3>.
Found 1-bit register for signal <one_line_req_end_d4>.
Found 1-bit register for signal <rd_buf_req_d0>.
Found 1-bit register for signal <rd_buf_req_d1>.
Found 1-bit register for signal <col_calu_state_idle_d0>.
Found 1-bit register for signal <H_scale_down>.
Found 1-bit register for signal <H_scale_up>.
Found 1-bit register for signal <pixel_data_read_en>.
Found 1-bit register for signal <pixel_data_read_en_d0>.
Found 8-bit register for signal <a_coff_V>.
Found 8-bit register for signal <b_coff_V>.
Found 24-bit register for signal <line0_pixel_data>.
Found 24-bit register for signal <line1_pixel_data>.
Found 1-bit register for signal <scale_data_out_V_d0>.
Found 24-bit register for signal <pixel_data0>.
Found 24-bit register for signal <pixel_data1>.
Found 8-bit register for signal <a_coff_H_from_V_d0>.
Found 8-bit register for signal <b_coff_H_from_V_d0>.
Found 1-bit register for signal <scale_data_en>.
Found 1-bit register for signal <scale_data_en_d0>.
Found 8-bit register for signal <a_coff_H>.
Found 8-bit register for signal <b_coff_H>.
Found 8-bit register for signal <a_coff_H_d0>.
Found 8-bit register for signal <b_coff_H_d0>.
Found 12-bit register for signal <pix_cnt>.
Found 1-bit register for signal <rd_req_d0>.
Found finite state machine <FSM_8> for signal <wr_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 16 |
| Inputs | 6 |
| Outputs | 5 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
INFO:Xst:1799 - State 0100 is never reached in FSM <scale_state>.
Found finite state machine <FSM_9> for signal <scale_state>.
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 13 |
| Inputs | 6 |
| Outputs | 6 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_10> for signal <rd_pixel_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 21 |
| Inputs | 8 |
| Outputs | 4 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_11> for signal <col_calu_state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 17 |
| Inputs | 7 |
| Outputs | 3 |
| Clock | sys_clk (rising_edge) |
| Reset | rst_n (negative) |
| Reset type | asynchronous |
| Reset State | 0000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 12-bit subtractor for signal <wr_lines[11]_GND_55_o_sub_6_OUT> created at line 127.
Found 20-bit adder for signal <map_col_next> created at line 136.
Found 12-bit adder for signal <wr_cnt[11]_GND_55_o_add_37_OUT> created at line 279.
Found 12-bit adder for signal <rd_req_cnt[11]_GND_55_o_add_43_OUT> created at line 299.
Found 12-bit adder for signal <wr_lines[11]_GND_55_o_add_48_OUT> created at line 319.
Found 20-bit adder for signal <scale_map_line[19]_GND_55_o_add_70_OUT> created at line 398.
Found 12-bit adder for signal <rd_col[11]_GND_55_o_add_95_OUT> created at line 483.
Found 12-bit adder for signal <rd_col[11]_GND_55_o_add_117_OUT> created at line 562.
Found 12-bit adder for signal <map_col[19]_GND_55_o_add_127_OUT> created at line 603.
Found 12-bit adder for signal <map_col_next[19]_GND_55_o_add_131_OUT> created at line 618.
Found 12-bit adder for signal <scale_col[11]_GND_55_o_add_150_OUT> created at line 649.
Found 12-bit adder for signal <pix_cnt[11]_GND_55_o_add_192_OUT> created at line 774.
Found 4-bit 4-to-1 multiplexer for signal <wr_state_next> created at line 34.
Found 4-bit 4-to-1 multiplexer for signal <rd_pixel_state_next> created at line 71.
Found 12-bit comparator equal for signal <line_data_is_ready> created at line 127
Found 12-bit comparator greater for signal <rd_col[11]_GND_55_o_LessThan_97_o> created at line 483
Found 12-bit comparator equal for signal <rd_col[11]_map_col[19]_equal_129_o> created at line 603
Found 12-bit comparator equal for signal <rd_col[11]_map_col_next[19]_equal_133_o> created at line 618
Found 12-bit comparator equal for signal <rd_col[11]_map_col_next[19]_equal_137_o> created at line 619
WARNING:Xst:2404 - FFs/Latches <K_h_reg<15:9>> (without init value) have a constant value of 0 in block <scaler_2>.
WARNING:Xst:2404 - FFs/Latches <K_h_reg<9:9>> (without init value) have a constant value of 1 in block <scaler_2>.
WARNING:Xst:2404 - FFs/Latches <K_h_reg<9:2>> (without init value) have a constant value of 0 in block <scaler_2>.
WARNING:Xst:2404 - FFs/Latches <K_v_reg<15:9>> (without init value) have a constant value of 0 in block <scaler_2>.
WARNING:Xst:2404 - FFs/Latches <K_v_reg<9:9>> (without init value) have a constant value of 1 in block <scaler_2>.
WARNING:Xst:2404 - FFs/Latches <K_v_reg<9:2>> (without init value) have a constant value of 0 in block <scaler_2>.
Summary:
inferred 12 Adder/Subtractor(s).
inferred 290 D-type flip-flop(s).
inferred 5 Comparator(s).
inferred 13 Multiplexer(s).
inferred 4 Finite State Machine(s).
Unit <scaler_2> synthesized.

Synthesizing Unit <line_buf_scaler_2>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\video\line_buf_scaler.v".
WITDH_2K = 0
WARNING:Xst:647 - Input <wraddress<10:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <line_buf_scaler_2> synthesized.

Synthesizing Unit <dp_ram_6>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\dp_ram.v".
DATA_WIDTH = 8
MEM_SIZE = 1024
Set property "syn_ramstyle = block_ram" for signal <mem>.
Found 1024x8-bit dual-port RAM <Mram_mem> for signal <mem>.
Found 10-bit register for signal <read_addr>.
Summary:
inferred 1 RAM(s).
inferred 10 D-type flip-flop(s).
Unit <dp_ram_6> synthesized.

Synthesizing Unit <dp_ram_7>.
Related source file is "C:\Users\Think\Desktop\3.23\src\common_rtl\dp_ram.v".
DATA_WIDTH = 8
MEM_SIZE = 512
Set property "syn_ramstyle = block_ram" for signal <mem>.
Found 512x8-bit dual-port RAM <Mram_mem> for signal <mem>.
Found 9-bit register for signal <read_addr>.
Summary:
inferred 1 RAM(s).
inferred 9 D-type flip-flop(s).
Unit <dp_ram_7> synthesized.

Synthesizing Unit <div_19u_26u>.
Related source file is "".
Summary:
no macro.
Unit <div_19u_26u> synthesized.
INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Synthesize - XST" failed
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/top.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang_xst.xrpt is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/top.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang_xst.xrpt is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/top.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang_xst.xrpt is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/top.stx is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang_xst.xrpt is missing.
WARNING:ProjectMgmt - File C:/Users/Think/Desktop/3.23/par_xilinx/compute_shang.stx is missing.

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Registered: ‎04-02-2018

Re: Project with PmodCLP module cannot synthesize --INTERNAL_ERROR:Xst:cmain.c:3423:1.29

Sorry, I don't know how to find log files, just copy and paste。

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Registered: ‎07-21-2014

Re: Project with PmodCLP module cannot synthesize --INTERNAL_ERROR:Xst:cmain.c:3423:1.29

@mr_zhang

 

"Unit <div_19u_26u> synthesized."  -- is this an IP?

Can you try to disable 'Read Cores' options under XST-Synthesis settings and then launch a run?

 

Thanks

Anusheel

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