cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
14,186 Views
Registered: ‎04-28-2014

Read a text file and put data into the BRAM

Hi

 

I am working on a object recognition project and I need to put my image into the BRAM. So to achieve that I have converted my image into a input text file of array of bits(attached sample).

 

So I in VHDL I want to read the input file line by line and then put it into the BRAM where I am using state machines to increment my address and set the input data. My code is attached below
.

 

The issue is that I am not able to read data when I run the program on the board but I do read data if I simulate it. I am not sure if there is a way to fix this issue or its not possible at all or if there is a better way to do it.
 

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
use IEEE.std_logic_signed.all;
use std.textio.all;

entity bramfeed is
    port(
        clk_i     : in std_logic;
        rst_i      : in std_logic;
        read_i    : in std_logic;
        data_o    : out std_logic_vector(7 downto 0)
    );    
end bramfeed;

architecture Behavioral of bramfeed is

COMPONENT blk_mem_gen_v7_3 IS
  PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;

constant MEM_DEPTH : integer := 256;
signal sig_wea    :    std_logic_vector (7 downto 0) := (others => '0');
signal sig_ena    :    std_logic := '0';
signal sig_addra    :    std_logic_vector (31 downto 0);
signal sig_addra_w    :    std_logic_vector (31 downto 0);
signal sig_addra_r    :    std_logic_vector (31 downto 0);
signal sig_dina    :    std_logic_vector (63 downto 0);
signal sig_douta    :    std_logic_vector (7 downto 0);
signal sig_wr : std_logic := '0';    
signal i    :    integer range 0 to (255) := 0;
signal k    :    integer range 0 to (MEM_DEPTH - 1) := 0;
signal twoFF    :    std_logic_vector (7 downto 0) := (others => '1');

--variable sig_addr    :    std_logic_vector(31 downto 0);

--Use this signal to indicate when you are going to write to memory
signal writeToMem    :    std_logic := '0';

type state_type is (s0, s1, s2, s3, s4, s5);
signal curr_state, next_state    :    state_type;

begin

    process (clk_i, rst_i)
    begin
        if (rst_i = '1') then
            curr_state <= s5;
            sig_wea <= (others => '0');
            sig_ena <= '0';
            sig_addra <= (others => '0');
            sig_addra_w <= (others => '0');
            sig_addra_r <= (others => '0');
            sig_dina <= (others => '0');
            sig_douta <= (others => '0');
            sig_wr <= '0';
        elsif (rising_edge(clk_i)) then
            curr_state <= next_state;
        end if;
    end process;
    
    --STATE MACHINE PROCESS
    process (clk_i,curr_state) is
    file mif_file : text open read_mode is "input.txt";
    variable mif_line : line;
    variable temp_bv : bit_vector(7 downto 0);
--    variable i    :    integer range 0 to (MEM_DEPTH - 1) := 0;
--    variable k    :    integer range 0 to (MEM_DEPTH - 1) := 0;
    begin
        case curr_state is
            --Read from the text file
            when s5 =>
                next_state <= s0;
                i <= 0;
                k <= 0;            
            when s0 =>
                --file_open(mif_file, "C:\Users\aveneesh\Desktop\4601\ISE\readwrite\input.txt",READ_MODE);  
                --Make sure we are not writing to memory in this state
                sig_ena <= '0';
                sig_wea <= (others => '0');
                --for i in 0 to MEM_DEPTH-1 loop
                --wait until clk_i'event and clk_i='1';
                readline(mif_file, mif_line);
                read(mif_line, temp_bv);
                    --sig_wea <= "11111111";
                sig_addra <= std_logic_vector(to_signed(i, sig_addra'length));
                sig_dina <= std_logic_vector(to_signed(0, 56)) & to_stdlogicvector(temp_bv);
                data_o <= to_stdlogicvector(temp_bv);
                i <= i + 1;
                --If you've read all the values, then go to
                if (i > 255) then
                    next_state <= s2;
                    i <= 0;
                else
                --end loop;
                    next_state <= s1;
                end if;
            
            --Write to memory
            when s1 =>

                --Set write enable to high so it writes to memory
                sig_ena <= '1';
                sig_wea <= (others => '1');
                next_state <= S0;
            
            --Only enter this state when you've read everything from the txt file
            --Read from bram
            when s2 =>
                sig_ena <= '1';
                sig_wea <= (others => '0');
                sig_addra <= std_logic_vector(to_signed(k, sig_addra'length));

                if (k = 255) then
                    next_state <= s4;
                else
                    next_state <= s3;
                end if;
                
            when s3 =>
                k <= k + 1;
                next_state <= s2;
                
            when s4 =>
                sig_ena <= '0';
            
        end case;
            
    end process;

    
        port_to_memory    :    blk_mem_gen_v7_3 port map ( clka => clk_i,
                                                                 ena    => sig_ena,
                                                                 wea     => sig_wea,
                                                                 addra => sig_addra,
                                                                 dina  => sig_dina,
                                                                 douta => sig_douta
                                                                );
end Behavioral;

 

_________________________________-

 

Any help would be appreciated

 

Thanks

Aveneesh

0 Kudos
9 Replies
Highlighted
Xilinx Employee
Xilinx Employee
14,148 Views
Registered: ‎07-01-2010

Re: Read a text file and put data into the BRAM

Moving the post to Synthesis.
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
Highlighted
Historian
Historian
14,142 Views
Registered: ‎02-25-2008

Re: Read a text file and put data into the BRAM

So, apart from the two-process state machine fail,

 

How do you get your text file into the FPGA?

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
14,137 Views
Registered: ‎11-28-2007

Re: Read a text file and put data into the BRAM

Hi Aveneesh,

 

why do you want to write data to the memory like that?

The reason why synthesis and simulation don't behave in the same way is because they work fundamentally different.

 

In this case, how is the FPGA supposed to get access to the file that you want to read in?

You need to think in terms of I/O, LUTs, registers, BRAMs and DSPs....

You state-machine will be implemented into LUTs and FFs.

Your memory into BRAM.

How does the file access fit into this picture?

 

In this case, I think what you are looking for is initialized BRAM.

BRAM of which the contents are defined at or before synthesis.

 

When you generate the RAM using coregen, can't select the initialization file then?

There are also ways to change BRAM init values at later stages using the DATA2MEM ISE program, but it's cumbersome I would not recommend using it unless you have an embedded system.

 

If you need to change the contents of the memory often:

Have you considered that?

Using an embedded microblaze system to load the memory using one port of a true-dual port BRAM and the other port to read/write for your object recognition application.

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.
Highlighted
Visitor
Visitor
14,131 Views
Registered: ‎04-28-2014

Re: Read a text file and put data into the BRAM


@bassman59 wrote:

So, apart from the two-process state machine fail,

 

How do you get your text file into the FPGA?


Can you please explain, What you really mean by Two-process state machine fail.

This is how we were taught to use state machines at the university.

 

Thanks

Aveneesh

0 Kudos
Highlighted
Visitor
Visitor
14,129 Views
Registered: ‎04-28-2014

Re: Read a text file and put data into the BRAM


@driesd wrote:

Hi Aveneesh,

 

why do you want to write data to the memory like that?

The reason why synthesis and simulation don't behave in the same way is because they work fundamentally different.

 

In this case, how is the FPGA supposed to get access to the file that you want to read in?

You need to think in terms of I/O, LUTs, registers, BRAMs and DSPs....

You state-machine will be implemented into LUTs and FFs.

Your memory into BRAM.

How does the file access fit into this picture?

 

In this case, I think what you are looking for is initialized BRAM.

BRAM of which the contents are defined at or before synthesis.

 

When you generate the RAM using coregen, can't select the initialization file then?

There are also ways to change BRAM init values at later stages using the DATA2MEM ISE program, but it's cumbersome I would not recommend using it unless you have an embedded system.

 

If you need to change the contents of the memory often:

Have you considered that?

Using an embedded microblaze system to load the memory using one port of a true-dual port BRAM and the other port to read/write for your object recognition application.

 

 

Best regards

Dries


That makes sense, thanks for that. My major concern is that I want to load my image into memory when the program starts on the board, which is why I was trying to read the contents of the file(image) and store them in memory.

 

 

Since the next part of the program would then be reconizing shapes in the image that I am storing in the memory.

 

I don't really need to change the contents of the memory often but  I need multiple images, so i will need to use multiple BRAM's which is my another trouble because I am looking for parallization using the zedboard.

 

I am not sure how the "embedded microblaze system" works, I will look it up. Thanks for the advise.

 

Aveneesh

0 Kudos
Highlighted
Historian
Historian
14,110 Views
Registered: ‎02-25-2008

Re: Read a text file and put data into the BRAM


Can you please explain, What you really mean by Two-process state machine fail.

This is how we were taught to use state machines at the university.


Your university is teaching an obsolete design paradigm, based on the requirements of archaic tools, and which is prone to errors.

 

State machines require only one synchronous (clocked) process.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Anonymous
Not applicable
13,783 Views

Re: Read a text file and put data into the BRAM

I am having a similar requirement of reading a text file and storing it (one time) into fpga during startup. Can somebody provide me some vhdl code for this? I have written following code which i suppose is not going to help me in this purpose:

 

architecture Behavioral of chain is

type matimage is array (0 to 255, 0 to 255) of integer range 0 to 255;
signal image_array: matimage;
file infile : text is in "img.txt";
variable inline: line;
variable dataread1 : integer range 0 to 255;
variable indexx,indexy: integer range 0 to 255;

begin

readimage : process(clk)
L1: for indexy in 0 to 255 loop
   L2 : for indexx in 0 to 255 loop
      if rising_edge(clk) then
        if (not (endfile(infile)) then
        readline(infile, inline);
        read(inline, dataread1);
        image_array(inedxx,indexy) <=integer(dataread1);
        endoffile <='0';
        else
        endoffile <='1'; --set signal to tell end of file read file is reached.
        end if;
     end if;
   end loop L2;
end loop L1;
end process readimage;

end Behavioral;

0 Kudos
Highlighted
Visitor
Visitor
11,686 Views
Registered: ‎08-15-2014

Re: Read a text file and put data into the BRAM

There is no VHDL code for writing a file to your FPGA.

 

There are a lot of things you can do in simulation with one line of code that can't be done in the FPGA in a simple way. For example, the FPGA doesn't have your image file "sitting in its hard drive", or a CPU that will do fopen() or memcmpy() for you

 

If you want to write ONE file to a bitstream that'll be loaded WITH the FPGA .bit file then that's easily done

 

If you want to load a file to the FPGA while it's running, it can be as simple as: sending the file one bit at a time via a serial line that your computer drives (you'll have to wite some VHDL code to make it parallel and write it to the BRAM) , or as complicated as: having to instantiate a PCIe core, design a PCIe DMA engine, write drivers and software for your FPGA card.

0 Kudos
Highlighted
Visitor
Visitor
6,330 Views
Registered: ‎03-03-2014

Re: Read a text file and put data into the BRAM

Hi,

 

There are 2 ways to read a text file into FPGA. Please refer to this :


https://fpga4student.blogspot.com/2016/11/two-ways-to-load-text-file-to-fpga-or.html

 

Example loading text file into FPGA and running on FPGA: here

0 Kudos