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Observer
Observer
3,757 Views
Registered: ‎02-02-2017

Read part name from hdl

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Hello all,

I'm working in a desing that can run in 2 differents devices. According the device part selected in propierties, some defines in hdl changes. Can I read the part name from HDL?, something like that...

 

`ifdef _XC6SLX25
`define ADDRESS 8'hff
`else
`define ADDRESS 8'h0f
`end

 Thanks in advance!

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Teacher
Teacher
6,442 Views
Registered: ‎03-31-2012

Re: Read part name from hdl

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@pablo_trujillo you don't have to use a define for this. You can pass a generic/parameter to your code while you synthesize and then do a generate statement (or use a package) to define the proper ADDRESS constant based on the parameter. It would be much cleaner too.

 

(untested code follows)

 

module top #(PACKAGE) (...);

 

generate if package == "XC6LX25" begin: sp6lx25

  constant ADDRESS = 8'hFF;

else

  constant ADDRESS = 8'h0F;

endgenerate

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: Read part name from hdl

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No this is not supported . You can try using tcl script
Thanks and Regards
Balkrishan
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Observer
Observer
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Registered: ‎02-02-2017

Re: Read part name from hdl

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Thank you very much balkris!!
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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Read part name from hdl

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Hi @pablo_trujillo,

 

As balkris pointed out, you can try using tcl.

 

Not the exact requirement but for a quickie, something like this would help: the below code with fetch the xdc file as per the part used in the project. While the xdc located in d1 and d2 and the part compared is xa7a15tcsg325-1I.

 

set $origin_dir "."

set origin_proj_dir "[file normalize "$origin_dir/./d1"]"

set a [get_property part [current_project]]

set b xa7a15tcsg325-1I

if {"$a" == "$b"} {
read_xdc $origin_dir/./d1/Artix.xdc
} else {
read_xdc $origin_dir/./d2/Kintex.xdc
}

 

Regards,

Prathik

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Guide
Guide
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Registered: ‎01-23-2009

Re: Read part name from hdl

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You can definitely use a `define in your code.

 

The trick is to getting the macro properly defined.

 

I don't know how you are implementing your design - are you using scripting or the GUI? Are you using project mode or non-project mode?

 

If you are using the GUI in project mode, you are setting the part manually when you create the project. The part number is not available directly to the elaboration process of synthesis, but you can define define a macro using the project infrastructure.

 

In the "Project Manager" section go to "Project Settings" -> "Language Options" -> "Verilog Options" -> "Defines". Click the green plus sign (+) and fill in the Name and Value you want for the Verilog define. This define will then be used in both synthesis and implementation. So if you set the "Name" to  "_XC6SLX25" and the "Value" to anything (lets say 1) then your `ifdef in your code will work. If you want to unset it, then you need to go back through this process and delete the setting by selecting it in the Defines section of the Verilog Options and hit the - button (-).

 

If you are using scripting in project mode, then the same thing can effectively be accomplished by using the Tcl command

 

set_property verilog_define {_XC6SLX25=1} [current_fileset]

 

If you are using non-project batch mode, then it is a bit more complicated, but still possible...

 

Avrum

 

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Teacher
Teacher
6,443 Views
Registered: ‎03-31-2012

Re: Read part name from hdl

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@pablo_trujillo you don't have to use a define for this. You can pass a generic/parameter to your code while you synthesize and then do a generate statement (or use a package) to define the proper ADDRESS constant based on the parameter. It would be much cleaner too.

 

(untested code follows)

 

module top #(PACKAGE) (...);

 

generate if package == "XC6LX25" begin: sp6lx25

  constant ADDRESS = 8'hFF;

else

  constant ADDRESS = 8'h0F;

endgenerate

 

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Observer
Observer
3,609 Views
Registered: ‎02-02-2017

Re: Read part name from hdl

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Thanks to all. The easier way for me to change between two devices is using a parameter on top.

 

Thanks & regards!

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