09-26-2013 09:34 AM
Is it possible to read a file for initializing signal value in VHDL when synthesis?
The code could be like the following (please ignore the VHDL grammer error):
clk : std_logic,
di : in std_logic,
do : out std_logic,
architecture of xxx is
--function to read file
function get_file_value(file_name : string) return integer;
function get_file_value(file_name : string) return integer is
variable b : integer;
variable fn : FILE;
b := read_file(fn) --reading some data from file
return b; -- b is kind of content from the file.
----init a value from file content.
constant init_value : inteer = get_file_value("c:\data.txt");
wait until rising_edge(clk);
do <= init_value;
I tested above code and realised the function was run but no result read from that file.
Thanks in advance.
09-26-2013 11:54 AM
I'm not a VHDL expert, but you should be able to do what you want. Did you get any errors or warnings during synthesis? One thing I noticed is you used a backslash in the path name. I would expect you to get some sort of error or warning that the file wasn't found because of that. Even running in Windows, path names should have normal slashes, not backslashes.
09-27-2013 09:48 AM
10-09-2013 11:07 PM
Can you check the example in the XST synthesis user guide page 235?
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/xst_v6s6.pdfe and see if that helps?