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Observer
Observer
5,000 Views
Registered: ‎06-24-2011

Reading file in vhdl when synthesis

Is it possible to read a file for initializing signal value in VHDL when synthesis?

 

The code could be like the following (please ignore the VHDL grammer error): 

 

entity

port(

 clk : std_logic,

 di : in std_logic,

do : out std_logic,

.................

 

);

end entity

 

architecture of xxx is

 

--function to read file

function get_file_value(file_name : string) return integer;

function get_file_value(file_name : string) return integer is

   variable b : integer;

  variable fn : FILE;

begin

    open_file(fn, file_name)

    b := read_file(fn)  --reading some data from file

    return b;   -- b is kind of content from the file.

end function;

 

----init a value from file content.

constant init_value : inteer = get_file_value("c:\data.txt");

signal  xxxx;

 

begin

 

   process

   begin

       wait until rising_edge(clk);

       do <= init_value;

  end process;

 

end archetecture;

 

 

I tested above code and realised the function was run but no result read from that file. 

 

Thanks in advance.

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4 Replies
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Professor
Professor
4,992 Views
Registered: ‎08-14-2007

Re: Reading file in vhdl when synthesis

I'm not a VHDL expert, but you should be able to do what you want.  Did you get any errors or warnings during synthesis?  One thing I noticed is you used a backslash in the path name.  I would expect you to get some sort of error or warning that the file wasn't found because of that.  Even running in Windows, path names should have normal slashes, not backslashes.

-- Gabor
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Explorer
Explorer
4,980 Views
Registered: ‎12-22-2010

Re: Reading file in vhdl when synthesis

good ask
only i know is that you can do that in IP core for RAM
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Xilinx Employee
Xilinx Employee
4,957 Views
Registered: ‎07-01-2010

Re: Reading file in vhdl when synthesis

Hi,

 

Can you check the example in the XST synthesis user guide page 235?

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/xst_v6s6.pdfe and see if that helps?

 

Regards,

Achutha

 

 

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Observer
Observer
4,896 Views
Registered: ‎06-24-2011

Re: Reading file in vhdl when synthesis

Thanks a lot, Achutha.    That is exactly what I need.  I will try if it works.

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