09-20-2012 01:49 PM
We are coding a combinatorial circuit with feedback in Verilog.
In first stage there are 2 AND gates and outputs of those two gates are inputs to an XOR gate in the second stage. Then, the output of this is one of the inputs to the first AND gate in first stage. Remaining 3 inputs in first stage are left to the user. (normal non-feedback inputs).
How to implement this without getting an error/warning in synthesis report. (The warning we get is that it removes the output port which is used as the feedback).
Also, kindly let me know if there is any good material to learn about combinatorial logic circuits that involve feedback.
Thanks in advance,
09-20-2012 01:59 PM - edited 09-20-2012 02:00 PM
There are quite a few past threads discussing delay chains, ring oscillators, and pulse/glitch generators. You might want to search the forums to browse through these threads, if you have not already done so.
Time for a reality check. In the real world of FPGA hardware, there are no AND gates or XOR gates. There are LUTs. If you are endeavouring to design at the very most basic, primitive level of FPGA hardware, then you need to abandon all levels of abstraction -- including quaint notions of discrete logic gates.
-- Bob Elkind