cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
854 Views
Registered: ‎04-04-2018

Reg: Synthesis Error in Hamming Decoder Verilog Coding

module hamm_dec(rst,en,dec_in,dec_out,err_corrected);

input rst,en;

input [1:12]dec_in;

output reg[1:4]dec_out;

output [1:12]err_corrected;

reg [1:12]temp_err_corrected;

reg [1:12]temp;

reg [1:4]temp_out;

reg h_matrix[1:12][1:4];

integer i,j,k,l;

integer f1,f2,f3;

initial

begin

f1=$fopen("h_matrix.txt","r");

f3=$fopen("h_matrix_out.txt","w");

end

always @(rst or en or dec_in) begin

if (!rst) begin

dec_out <= 0;

temp <= 0;

temp_out <= 0;

temp_err_corrected <= 0;

end else if (rst && !en)begin

temp_err_corrected <= dec_in;

for (i=1;i<=12;i=i+1)

begin

for (j=1;j<=4;j=j+1)

begin

f2=$fscanf(f1,"%b",h_matrix[i][j]);

end


end

end else begin

for (k=1;k<=4;k=k+1)

begin

for (l=1;l<=12;l=l+1)

begin

temp[l] = dec_in[l] & h_matrix[l][k];

temp_out[k] = ^temp;

end

end

dec_out <= temp_out;

temp_err_corrected[temp_out] <= ~(dec_in[temp_out]);

end

end

assign err_corrected=temp_err_corrected;

endmodule

 

Error:

Analyzing top module <hamm_dec>.

ERROR:Xst:2333 - "../../../../../shilpha.G/FFT CODING/Hamming_code/hamm_dec.v" line 57: File argument of function $fscanf is not constant.

ERROR:Xst:2634 - "../../../../../shilpha.G/FFT CODING/Hamming_code/hamm_dec.v" line 66: For loop stop condition should depend on loop variable or be static.

WARNING:Xst:905 - "../../../../../shilpha.G/FFT CODING/Hamming_code/hamm_dec.v" line 33: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <f1>

0 Kudos
1 Reply
anusheel
Moderator
Moderator
807 Views
Registered: ‎07-21-2014

vincybeaulah@1 Please do not post same query multiple times.

 

Thanks

Anusheel

0 Kudos