UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer aparna
Observer
6,268 Views
Registered: ‎10-17-2011

Regarding modulus and division operators

Hi

Can I please get some help with this code?

 

Its simple but I am not able to use modulus operator or the division operator?

 

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

use IEEE.NUMERIC_STD.ALL;

 

entity modcheck is
Port ( a : in STD_LOGIC_vector(3 downto 0):="1000";
b : in STD_LOGIC_vector(3 downto 0):="1100";
c : out STD_LOGIC_vector(3 downto 0));
end modcheck;

 

architecture Behavioral of modcheck is

 

signal p,q:integer;

 

begin
p<=conv_integer(a);
q<=conv_integer(b);
c<=a mod b;

end Behavioral;

 

 

Is there a reason i am unable to use this modulus operator? are there any library files missing?

Pl lemme know

 

Thanks a ton 

Aparna:)

0 Kudos
4 Replies
Historian
Historian
6,265 Views
Registered: ‎02-25-2008

Re: Regarding modulus and division operators


@aparna wrote:

Hi

Can I please get some help with this code?

 

Its simple but I am not able to use modulus operator or the division operator?

 

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

use IEEE.NUMERIC_STD.ALL;

 

entity modcheck is
Port ( a : in STD_LOGIC_vector(3 downto 0):="1000";
b : in STD_LOGIC_vector(3 downto 0):="1100";
c : out STD_LOGIC_vector(3 downto 0));
end modcheck;

 

architecture Behavioral of modcheck is

 

signal p,q:integer;

 

begin
p<=conv_integer(a);
q<=conv_integer(b);
c<=a mod b;

end Behavioral;

 

 

Is there a reason i am unable to use this modulus operator? are there any library files missing?

Pl lemme know

 

Thanks a ton 

Aparna:)


First of all, don't use std_logic_arith, and don't use conv_integer. You should use the numeric_std functions (you've already used numeric_std, anyway).

 

p <= to_integer(unsigned(a);

q <= to_integer(unsigned(b);

 

Next, the integers p and q should be ranged; otherwise, they're 32 bits which might be too big.

 

Third, you convert a and b to integers p and q, yet your mod operation is on a and b. That seems like a mistake.

 

Finally, to actually answer your question. Read the fine synthesis guide. The division and mod operators are not supported except when the divisor (q) is a power-of-two. Furthermore, I haven't used the mod operator for anything other than to ensure that counters roll over properly, so I'm not sure if the result of a mod operation like you're doing will synthesize.

----------------------------Yes, I do this for a living.
Teacher rcingham
Teacher
6,247 Views
Registered: ‎09-09-2010

Re: Regarding modulus and division operators

I heartily concur with bassman59's wise words.

Furthermore, for synthesis (at least up to 13.2) the second parameter of the 'mod' operator must be a CONSTANT value, which restriction is currently causing me considerable grief.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Xilinx Employee
Xilinx Employee
6,237 Views
Registered: ‎08-17-2011

Re: Regarding modulus and division operators

Recently there's been other posts about div & mod operations...
- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Historian
Historian
6,231 Views
Registered: ‎02-25-2008

Re: Regarding modulus and division operators


@rcingham wrote:
I heartily concur with bassman59's wise words.

Furthermore, for synthesis (at least up to 13.2) the second parameter of the 'mod' operator must be a CONSTANT value, which restriction is currently causing me considerable grief.

Just as a datapoint, Synplify also requires the second parameter of mod to be a constant. Synthesizing a non-constant divisor probably gets very icky very quickly.

----------------------------Yes, I do this for a living.
0 Kudos