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Visitor carlmgmt
Visitor
10,181 Views
Registered: ‎04-27-2015

Register clock enable synthesis/implementation on Vivado

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Hello.

I'm using Vivado 2014.4 for design implementation of VHDL code on a Artix-7 FPGA (XC7A35T CSG324-1). I see what I think it's a odd way of synthesizing registers with clock enable (default options are used for synthesis and implementation).

A simple code for a 1 bit register with clock enable as:

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;  
 
  entity top is
      port (
        clk_i        : in    std_logic;
        en_i        : in    std_logic;
        data_i     : in    std_logic;
        data_o   : out  std_logic  
      );
  end entity top;
 
  architecture arch of top is
 
  begin
 
    process(clk_i)
    begin
      if (rising_edge(clk_i)) then      
        if (en_i='1') then
          data_o  <= data_i;
        end if;
      end if;
    end process;
    
  end architecture arch;
 
generates a FF+LUT. FF clock enable input is not used (set to 1) and input data to register is created based on en_i, data_i and register output data_o.

Attached you can see schematic of final circuit (after implementation).

Am I missing something? Do you know whether any option/constraint should be used for clock enable inference?

Best regards,

 Carlos

 

Schematic_register.jpg
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1 Solution

Accepted Solutions
Moderator
Moderator
18,494 Views
Registered: ‎07-21-2014

Re: Register clock enable synthesis/implementation on Vivado

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Hi,

 

Use DIRECT_ENABLE attribute on the input.


Apply DIRECT_ENABLE on an input port or other signal to have it go directly to the enable line of a flop when there is more than one possible enable or when you want to force the synthesis tool to use the enable lines of the flop.
The DIRECT_ENABLE attribute can be placed on any port or signal.

Example

entity test is port(
in1 : std_logic_vector (8 downto 0);
clk : std_logic;
ena1, ena2, ena3 : in std_logic
out1 : std_logic_vector(8 downto 0));
attribute direct_enable : string;
attribute direct_enable of ena3: signal is "yes";
end test;

 

Thanks,
Anusheel
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4 Replies
Moderator
Moderator
18,495 Views
Registered: ‎07-21-2014

Re: Register clock enable synthesis/implementation on Vivado

Jump to solution

Hi,

 

Use DIRECT_ENABLE attribute on the input.


Apply DIRECT_ENABLE on an input port or other signal to have it go directly to the enable line of a flop when there is more than one possible enable or when you want to force the synthesis tool to use the enable lines of the flop.
The DIRECT_ENABLE attribute can be placed on any port or signal.

Example

entity test is port(
in1 : std_logic_vector (8 downto 0);
clk : std_logic;
ena1, ena2, ena3 : in std_logic
out1 : std_logic_vector(8 downto 0));
attribute direct_enable : string;
attribute direct_enable of ena3: signal is "yes";
end test;

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

Visitor carlmgmt
Visitor
10,163 Views
Registered: ‎04-27-2015

Re: Register clock enable synthesis/implementation on Vivado

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Anusheel, many thanks for your quick reply.

 

Regards,

 

 Carlos

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Visitor filgiorgi
Visitor
3,000 Views
Registered: ‎09-08-2014

Re: Register clock enable synthesis/implementation on Vivado

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Thanks, I didn't know how to force tha use of CE.

Anyway, if it may be of some help, the synthesis tool seems to be reluctant in using CE when the datapath of D is a loopback combinatorial logic of Q, as I see from the schematic you posted. I just made a post here about that.

https://forums.xilinx.com/t5/General-Technical-Discussion/using-clock-enable/m-p/776338#M39599

F.

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Observer josyb
Observer
2,016 Views
Registered: ‎05-13-2015

Re: Register clock enable synthesis/implementation on Vivado

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Actually the OP's original post only has a feed-back from Q to D, because Vivado didn't implement the CE

I stumbled on the same issue while I was looking for a strange generated loop (output of LUT back to input). While expanding the schematic around that I noticed that Vivado doesn;t always implement a CE where I expected it to.

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