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Contributor
Contributor
307 Views
Registered: ‎09-20-2017

Resource utilization per signal

Hi,

is there a way to get the resource utilization on a per signal basis? 
I mean, if there are a few bad coded lines, Vivado will report net xy needs about 5000 CLBs? 

Thanks

Franz

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5 Replies
Moderator
Moderator
303 Views
Registered: ‎11-04-2010

Re: Resource utilization per signal

Hi, @franzforstmayr , 

Vivado can report the module level utilization, and it's an odd requirement to report utilization based on nets. 

You can try to report the cells driven by the net.

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Contributor
Contributor
206 Views
Registered: ‎09-20-2017

Re: Resource utilization per signal

I'll have to try this out!

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Scholar dgisselq
Scholar
193 Views
Registered: ‎05-21-2015

Re: Resource utilization per signal

When optimizing pieces of code, I will often separate that code into a module by itself and run Yosys on it with the following script:

read -sv module.v
synth_xilinx
stat

That will return a good estimate of the resources used by the module, without needing to connect all of the various exterrnal wires/ports up to valid external pins, and also without needing to specify which 7-series part you are using.

Dan

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Moderator
Moderator
175 Views
Registered: ‎11-04-2010

Re: Resource utilization per signal

Hi, @dgisselq ,

It seems synthesizing the single sub-module one-by-one isn't efficient enough when you have hundreds of modules in your design. 

You can also check the result of report_utilization of the top design to get the similar information.

 

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Moderator
Moderator
152 Views
Registered: ‎07-21-2014

Re: Resource utilization per signal

@franzforstmayr 

I would prefer to look into the synthesis log file to check for warnings and info. In many scenarios, the tool will write a message in the log file when an incorrect coding style is used. For example, bad memory code may result in " too sparse and won't be mapped to RAM"

 

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