05-09-2019 09:15 AM
is there a way to get the resource utilization on a per signal basis?
I mean, if there are a few bad coded lines, Vivado will report net xy needs about 5000 CLBs?
05-09-2019 09:24 AM
Hi, @franzforstmayr ,
Vivado can report the module level utilization, and it's an odd requirement to report utilization based on nets.
You can try to report the cells driven by the net.
06-25-2019 05:10 AM
When optimizing pieces of code, I will often separate that code into a module by itself and run Yosys on it with the following script:
read -sv module.v synth_xilinx stat
That will return a good estimate of the resources used by the module, without needing to connect all of the various exterrnal wires/ports up to valid external pins, and also without needing to specify which 7-series part you are using.
06-25-2019 08:24 AM
Hi, @dgisselq ,
It seems synthesizing the single sub-module one-by-one isn't efficient enough when you have hundreds of modules in your design.
You can also check the result of report_utilization of the top design to get the similar information.
06-28-2019 01:17 AM
I would prefer to look into the synthesis log file to check for warnings and info. In many scenarios, the tool will write a message in the log file when an incorrect coding style is used. For example, bad memory code may result in " too sparse and won't be mapped to RAM"