02-15-2018 11:06 PM
Hello,
I am using Vivado 2017.3.1
As soon as enable Retiming in Synthesis, Synthesis fails with
TclStackFree: incorrect freePtr. Call out of sequence?
I cant upgrade to 2017.4 for some reason.I am going ahead without using the retiming option.
Thanks,
Sachin B
02-16-2018 06:05 PM
Hi @sachinb_apt1,
Do you have a test-case that we can try?
Regards,
Prathik
-----------------------------------------------------------------------------------------------
Please mark the appropriate post as an answer "Accept as solution" in case it helps to resolve your query.
Give Kudos to a post which you think is helpful and reply oriented.
-----------------------------------------------------------------------------------------------
02-19-2018 01:13 AM
02-19-2018 01:18 AM
Can you share vivado log and hs_err_pid* files to ahve a look?
It will be helpful if you can provide testcase to debug and provide you a workaround.
Thanks,
Manusha
02-19-2018 01:33 AM
The attachment's hs_err_pid96778.log content type (text/x-log) does not match its file extension and has been removed.
The attachment's hs_err_pid96904.log content type (text/x-log) does not match its file extension and has been removed.
The attachment's runme.log content type (text/x-log) does not match its file extension and has been removed.
02-19-2018 01:41 AM
02-19-2018 01:42 AM
02-19-2018 04:03 AM
Is there a set_param in vivado, with which we can enable either the forward or backward register balancing like we would do them in ISE?
Well what i really trying to get register balancing done using some micro level switches instead of a macro level retiming switch.
Also let me know if there is way to apply retiming switch to certain module or instance?
Thanks,
Sachin B
02-19-2018 09:56 PM
Hi @pulim
I suspect if a Combinatorial loop in GT logic is causing it.
The powergood signal generation in the GTY IP has a combinatorial loop. Which is mentioned in the runme log file i posted
See the snapshot attached.
Also let me know if there was a way to apply retiming to specific instance (and downstream) instead of entire design.
02-19-2018 10:03 PM
I did a quick search with the crash log but didnt find any known issues with similar log.
Can you share the project so that I can debug and report this to development team?
You can apply re-timing to specific module instead of entire design uisng block level synthesis.
Please check below.
set_property BLOCK_SYNTH.RETIMING 1 [get_cells <instname>]
For more details on block level synthesis refer to chapter 3 in UG901.
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf
02-19-2018 11:26 PM
Well with the block level
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
Numbers of forward move = 0, and backward move = 0
So pretty much it passed the synthesis but did not do any register balancing.
And not sure what such messages in synth log
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
Total number of crtical paths = 0
During Synthesis the tool probably thinks there are no critical path and hence it did not do any register balancing.
However my post synthesis Negative Slack is -1.136 ns for the block i did the retiming with 16 levels of logic.
How did during synthesis/Retiming the tool saw not even a single path critical. Strange.
I tried creating a sharable testcase but it doesnt fail retiming in sub block level.
So cannot share the project.
Closing Comments for now--- Whether a tool does the retiming on some block or not, it should not crash the way it is.