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tcuong141
Observer
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Registered: ‎02-24-2016

Retiming option of Synthesis

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Hi all,

 

I am going to use retiming option of Synthesis Vivado2016.1. I have a point not clearly about it.

My query is about latency of circuit after retiming, Ex, If I had one combinational logic between two D-Flipflop, when retiming had done, how latency were from input to output ?

 

 

Thanks all,

Tan Cuong

 

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nagabhar
Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

HI @tcuong141

 

Retiming option only moves the existing register across comb logic. and do not insert new registers and hence latency of the circuit does not change with retiming.

 

-retiming: This boolean option <on|off> provides an option improve circuit performance for intra-clock sequential paths by automatically moving registers (register balancing) across combinatorial gates or LUTs. It maintains the original behavior and latency of the circuit and does not require changes to the RTL sources. The default is off.

 

 

refer page 11 of UG901
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug901-vivado-synthesis.pdf

 

Thanks
Bharath
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vijayak
Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Hi @tcuong141

It maintains the original behavior and latency of the circuit and does not require changes to RTL.

 

i.e the latency will not be changed with retiming.

Retiming is an option improve circuit performance for intra-clock sequential paths by automatically moving registers
(register balancing) across combinatorial gates or LUTs.

Thanks,Vijay
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tcuong141
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Thanks Vijay,

 

Can I ask more question ?

I have checked ug835-vivado-tcl-commands (v2016.1), I saw "retime" option of phys_opt_design.

What is different between "retiming" option of Synthesis and "retime" option of phys_opt_design ?

Will "retime" option of phys_opt_design maintain the original behavior and latency of the circuit ?

 

Thanks,

Tan Cuong

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
Register balancing or Retiming enables a flip-flop retiming algorithm in the Vivado synthesis process.

Retiming will improve the design timing performance by moving flip-flops and latches across the logic to increase clock frequency.

Starting with Vivado 2015.3, retiming can be enabled in Vivado synthesis using the following Tcl command:

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter synRetiming true"

Starting from Vivado 2016.1, a new option "-retiming" is added into Synthesis settings and synth_design command as a formal support of retiming.
Thanks and Regards
Balkrishan
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arpansur
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Registered: ‎07-01-2015

Hi @tcuong141,

 

To understand regarding retime option in synthesis please go through http://www.xilinx.com/support/answers/65410.html.

In implementation-> phys_opt_design retime option re-time the registers forward through combinational logic to balance path delays. The delays calculated in implementation are more accurate. 

Thanks,
Arpan
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tcuong141
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Registered: ‎02-24-2016

Hi Arpan,

 

In Implementation, Do you mean that the latency of the circuit will be not change by "retime" option ?

If the original circuit has two D-Flipflop, will the latency of circuit be two clock cycles when "retime" option has done ?

 

 

Thanks ,

Tan Cuong

 

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nagabhar
Xilinx Employee
Xilinx Employee
13,955 Views
Registered: ‎05-07-2015

HI @tcuong141

 

Retiming option only moves the existing register across comb logic. and do not insert new registers and hence latency of the circuit does not change with retiming.

 

-retiming: This boolean option <on|off> provides an option improve circuit performance for intra-clock sequential paths by automatically moving registers (register balancing) across combinatorial gates or LUTs. It maintains the original behavior and latency of the circuit and does not require changes to the RTL sources. The default is off.

 

 

refer page 11 of UG901
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug901-vivado-synthesis.pdf

 

Thanks
Bharath
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tcuong141
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Registered: ‎02-24-2016
It seem clear now.

Thanks all,
Tan Cuong
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