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Adventurer
Adventurer
2,759 Views
Registered: ‎05-12-2017

Running synthesis of SystemVerilog from commandline

I'm trying to figure out how to run synthesis of SV from commandline. I've tried various combination of options unsuccessfully.

 

If it helps I tried to use xst bundled with Vivado 2017.2.

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5 Replies
Voyager
Voyager
2,754 Views
Registered: ‎06-24-2013

Re: Running synthesis of SystemVerilog from commandline

Hey @mpiechotka,

 

I'm trying to figure out how to run synthesis of SV from commandline.

I've tried various combination of options unsuccessfully.

Not sure where the problem is ...

 

Vivado has the read_verilog command which can be given the -sv option to treat the source as SystemVerilog (details can be found in UG835).

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Voyager
Voyager
2,747 Views
Registered: ‎06-24-2013

Re: Running synthesis of SystemVerilog from commandline

Hey @mpiechotka,

 

I just saw the 'xst' note, so to clarify, I wanted to add that Xilinx ISE does not support SystemVerilog at all.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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Adventurer
Adventurer
2,743 Views
Registered: ‎05-12-2017

Re: Running synthesis of SystemVerilog from commandline

@hpetzl Oh. I see - so I need to create a tcl script and use Vivado in batch mode.
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Voyager
Voyager
2,729 Views
Registered: ‎06-24-2013

Re: Running synthesis of SystemVerilog from commandline

@mpiechotka: Yep, that's the way it works with Vivado now.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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Moderator
Moderator
2,553 Views
Registered: ‎11-09-2015

Re: Running synthesis of SystemVerilog from commandline

Hi @mpiechotka,

 

You don't have to create a script you can do it in tcl mode but it is better with a script if you need to re-do stuffs


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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