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Visitor
Visitor
855 Views
Registered: ‎02-01-2018

SV Synthesis Issue (struct compare within a loop)

The attached code results in incorrect synthesis results.  We have narrowed this down to the comparison of SV structs within a loop.  In this example, detect[0] and detect[2] should be the same and detect[1] and detect[3] should be the same.  However, in the synthesized results, detect[1] and detect[3] are not the same (detect[3] is correct).  detect[0] and detect[2] are the same but both provide incorrect comparisons.  By eliminating the loop, these comparisons will be performed correctly.

 

We are using Vivado 2017.4.1 for these tests.

 

Can someone please confirm these results?

 

Thanks.

 

 

3 Replies
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Scholar
Scholar
846 Views
Registered: ‎09-16-2009

Re: SV Synthesis Issue (struct compare within a loop)

 

I've confirmed this RTL / netlist mismatch on my end with Vivado 2017.1.

I've tweaked the testcase a bit (removed symbol[3:2] inputs since they weren't used and just clutter the logs).

 

typedef struct {
    logic       kchar;
    logic [7:0] sym;
} tTEST_STRUCT;

const tTEST_STRUCT kCOMPARE_STRUCT = '{1'b1, 8'h1c};

module foo7_test ( // core clock domain input logic lnk_clk, // link clock input logic lnk_reset, // link domain reset input logic fct_enable, input tTEST_STRUCT symbol [1:0], // lane symbol stream input output logic [3:0] detect, output wire [ 1 : 0 ] check ); int fx; always_comb begin : TestCode if (fct_enable == 1'b0) begin detect = 4'b0000; end else begin for (fx = 0; fx < 2; fx++) begin detect[fx] = (symbol[fx] == kCOMPARE_STRUCT) ? 1'b1 : 1'b0; end // loop detect[2] = (symbol[0] == kCOMPARE_STRUCT) ? 1'b1 : 1'b0; detect[3] = (symbol[1].kchar == 1'b1 && symbol[1].sym == 8'h1c) ? 1'b1 : 1'b0; end // if end : TestCode assign check[ 0 ] = detect[2] == detect[0]; // Should optimize to constant 1 assign check[ 1 ] = detect[3] == detect[1]; // Should optimize to constant 1 endmodule

The check outputs make the miscompare obvious.

 

This is a Vivado synthesis bug, IMHO, and should be fixed.  LEC should show the difference easily.

 

A note, I did make one change to get the testcase to pass.  I changed the structure to a packed structure, by JUST adding the "packed" modifier to the struct.  Doing that, it will compare.  Not that this changes the validity of the testcase - Vivado's doing the wrong thing here, and this should be fixed.

 

I'm actually shocked that we've not stumbled on the bug yet.  We're using structures, and arrays in SystemVerilog with Vivado all over the place.  Hard to believe we didn't encounter this ourselves.  Good catch, and good testcase.

 

Regards,

 

Mark

 

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Xilinx Employee
Xilinx Employee
823 Views
Registered: ‎07-21-2014

Re: SV Synthesis Issue (struct compare within a loop)

Hello,

Thanks for pointing out the bug. I have reproduced it at my end and will report this issue to the factory.

-Shreyas
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Moderator
Moderator
762 Views
Registered: ‎07-21-2014

Re: SV Synthesis Issue (struct compare within a loop)

@cjruggiero

 

CR-998946 was reported for this bug.

 

Thanks

Anusheel

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