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Registered: ‎01-30-2014

Schematic optimization using synthesis attributes


I have a problem on the schematic obtained by the synthesis for two different types of memory. I premise that I am synthesizing on a Virtex 7.
I briefly descriped my problem:
Two modules: module_lattice module_buffer.

- The module "module_lattice" contains a single lattice with a dimension of 100*100 bits and this module is instantiated twice. The lattice is declared as: (*keep = "true"*) reg [99:0] lattice [99:0];


- The module "module_buffer" contains a memory formed by 26*1000 bits and the module is instantiated just once. This memory is declared as: (*keep = "true"*) reg [25:0] buffer [999:0];. In addition, this module presents the attribute (*dont_touch = "true"*) before its declaration, otherwise the entire module is trimmed away (and i can't understand why). 

The two lattices declared before don't show any type of problem and they are assigned to RAM blocks in the schematic; the buffer, instead, slows down everything, without using any RAM instantiation. When I expand the module_buffer in the schematic view (it takes several minutes), it shows a more than huge entanglement of wires among FDRE flip flops. 
I've also tried to move the (*dont_touch = "true"*) on the level above which instantiates module_lattice and also using the attribute (*ram_style = "block"*) but nothing seems work. Here some images:


Here the lattice's RAM:lattice.png

The entanglement: entanglement.png

The buffer flip flops: flipflop.png


Any suggestion?

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Xilinx Employee
Xilinx Employee
Registered: ‎04-16-2012

Re: Schematic optimization using synthesis attributes


Compare the RAM code between two modules. i.e., module_lattice, module_buffer.
Also can you post the module_buffer code here?

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