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Observer trungnguyen
Observer
235 Views
Registered: ‎05-04-2018

Sensitivity list problem in synthesis - Vivado

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Hello all,

I have one question regarding the sensitivity list problem.

As I understand, sensitivity list as we write in code (VHDL) is just for behavior simulation.

When synthesizing code, the tool will automatically finding trigger signals for FSM based on condition statements. Is that right?

In my case, I have a piece of code like following:

state_logic: process(pre_state)
begin
case pre_state is
    when RESET =>
        send_cmd           <= '0';
        index              <= 0;
        nx_state           <= INIT;
        timer              <= 0;
        db_state_value     <= "000";
         
    when INIT => 
        send_cmd         <= '0';
        nx_state         <= SET_ANTENNA_INDEX;
        timer            <= SWITCH_PERIOD;
        db_state_value   <= "001";
        
    when SET_ANTENNA_INDEX =>
        send_cmd         <= '0';
        timer            <= 0;
        if (index   = NUM_ANTENNA - 1) then
            nx_state     <= UPDATE_INDEX_0;
        else
            nx_state     <= UPDATE_INDEX_1;
        end if;
        db_state_value   <= "010";
    
    when UPDATE_INDEX_0 =>
        nx_state         <= ENABLE_CMD;
        index            <= 0;
        db_state_value   <= "111";
        
    when UPDATE_INDEX_1 =>
        nx_state         <= ENABLE_CMD;
        index            <= index + 1;
        db_state_value   <= "110";
        
    when ENABLE_CMD =>
        send_cmd         <= '1';
        timer            <= 0;
        nx_state         <= INIT;
        db_state_value   <= "011";

    when OTHERS => 
        send_cmd         <= '0';
        index            <= 0;
        nx_state         <= INIT;
        timer            <= 0;   
        db_state_value   <= "100";
end case;
end process state_logic;

In bev simulation, everything seems to be fine.

But when performing post-synthesis simulation, value of "index" increases continuously in state UPDATE_INDEX_1.

I think the cause of the problem here is: tool automatically include "index" into its sensitivity list or trigger event for FSM. That's why state UPDATE_INDEX_1 is called immediately once index changes.

So my question is:

- Can we turn off the feature of auto insert sensitivity list of synthesis tool?

- OR could you suggest me any coding style to overcome this problem?

 

Thanks in advance.

Trung Nguyen

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1 Solution

Accepted Solutions
Scholar u4223374
Scholar
216 Views
Registered: ‎04-26-2015

Re: Sensitivity list problem in synthesis - Vivado

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(1) The hardware cannot implement what you are asking for. For combinational blocks (like this one), the rule is that every signal used as an input in the block must be in the sensitivity list - check how combinational circuits work to see why this must be the case in hardware. If you could "turn off" this functionality in the synthesis tool, it'd just be unable to build the design at all (because what you want is incompatible with what the hardware can do).

(2) The fix is to investigate sequential logic. Sequential logic allows you to have a sensitivity list that does not cover all inputs - normally the sensitivity list is just the clock signal, or sometimes the clock signal and a reset too (if you're using asynchronous resets), and the hardware can implement this.

2 Replies
Scholar u4223374
Scholar
217 Views
Registered: ‎04-26-2015

Re: Sensitivity list problem in synthesis - Vivado

Jump to solution

(1) The hardware cannot implement what you are asking for. For combinational blocks (like this one), the rule is that every signal used as an input in the block must be in the sensitivity list - check how combinational circuits work to see why this must be the case in hardware. If you could "turn off" this functionality in the synthesis tool, it'd just be unable to build the design at all (because what you want is incompatible with what the hardware can do).

(2) The fix is to investigate sequential logic. Sequential logic allows you to have a sensitivity list that does not cover all inputs - normally the sensitivity list is just the clock signal, or sometimes the clock signal and a reset too (if you're using asynchronous resets), and the hardware can implement this.

Observer trungnguyen
Observer
190 Views
Registered: ‎05-04-2018

Re: Sensitivity list problem in synthesis - Vivado

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Thanks for very helpful advise.
My solution is putting "index" in the sequential logic to avoid unexpected triggers as your 2nd suggestion.
Trung Nguyen
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