02-20-2019 07:25 AM
I want to create a regular structure of multipliers. My idea is automatically place DSP from HDL code. I have DSP block described in the RTL code (simplified code for example):
signal b : signed(17 downto 0); signal d : signed(26 downto 0); signal mul : signed(44 downto 0); signal acc : signed(47 downto 0); ... process(clk) begin if rising_edge(clk) then b <= signed(data(17 downto 0)); d <= signed(data(39 downto 13)); mul <= b*d; acc <= acc + mul; end if; end process;
It is infered to DPS48E2 with all registers packed into the one. Now I want to fix DSP location via LOC attribute. But there are no results. It seems that signals lost location attribute after optimization. I tried to set attribute to signals mul and acc or to a whole entity at top level.
attribute LOC : string; attribute LOC of acc:signal is "DSP48E2_X1Y1";
Also I tried to set DONT_TOUCH attribute but it breaks packing registers to DSP without any positive effect.
I don't want to set location to netlist cells via XDC. Is there any way to set location directly from HDL? Thank you.
02-20-2019 07:44 AM
There are two ways you can set the LOC attribute. If you want to do it in the RTL, then you need to set the LOC attribute on the label of the DSP48 instance. There's no direct way to do it on an inferred DSP48. It has to be instantiated.
The second way is to place the LOC attribute as a set_property command in the XDC, using the full or partial hierarchical path to the DSP48 primitive. This method is quite fragile, since if you modify the hiearchy, or fiddle with the code too much, the path will change.
02-20-2019 08:35 AM
Is there any particular reason you want to LOC your DSPs? doing so renders the code much less portable, and it is rare that you would achieve better results than the compiler.
02-20-2019 11:22 AM
It is intended for test project with 90-100% resource usage to test power subsystem of developed board. A have another version of such project without LOCs and it needs about 20 hours to build. Design with FFs only which were fixed compiles in 2 hours ;) So, I'm planning to instantiate DSP and BRAM manually...
02-21-2019 12:23 AM