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Observer
Observer
10,115 Views
Registered: ‎07-09-2014

Shorthand notation for output signals

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Hello, I wonder if there is a way in Verilog  to abbreviate output signals. I have a design module that has 1024 10-bit registers that need to be sent to other modules, it is simply too tedious to list them all out, not to mention about being error prone, is it possible to use Generate to declare these output signals or something like that? I have tried to search for similar examples without success.

 

Thanks in advance!

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Guide
Guide
19,454 Views
Registered: ‎01-23-2009

To get register "i" you would use

 

control_reg_o[i*10 +: 10]

 

This uses the variable part select syntax in Verilog, and is fully supported in any Verilog-2001 compliant synthesis tool or simulator (which all Xilinx products are).

 

The first example will work in SystemVerilog only. But Vivado fully supports SystemVerilog - you just need to turn on the SystemVerilog flag for the files in question (ISE does not support SystemVerilog, except through external synthesis and simulation tools).

 

Avrum

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Moderator
Moderator
10,113 Views
Registered: ‎07-01-2015

Hi @hphung,

 

Are you talking about in and out port declaration?

If so I am not sure if this is an acceptable workaround:

You can write a Tcl script to generate the out port syntax and paste it in RTL.

 

Thanks,
Arpan

Thanks,
Arpan
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Scholar
Scholar
10,106 Views
Registered: ‎09-16-2009

That's a LOT of registers.  It's going to take a significant amount of resources just for them!  That's a lot of flip-flops.

 

In any event, I'd declare them in one line.  Array's are your friend.

 

output wire [ 1023 : 0 ] [ 9 : 0 ] control_reg_o

 

Done!

 

If you don't wish to use SystemVerilog, then a slightly modified Verilog-2001 form:

output wire [ ( 1024 * 10 ) - 1 : 0 ] control_reg_o

 

Regards,

 

Mark

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Observer
Observer
10,095 Views
Registered: ‎07-09-2014

Yes, this is for the output port declaration. If all else fails, I will have to take up on your suggestion. Thanks.

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Observer
Observer
10,094 Views
Registered: ‎07-09-2014

Hi Mark,

 

I read somewhere that one cannot pass the array out to other modules, but I could be wrong.

Your second suggestion may work, but I just don't know how to address each of these registers, please give an example, thanks.

 

Hue

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Guide
Guide
19,455 Views
Registered: ‎01-23-2009

To get register "i" you would use

 

control_reg_o[i*10 +: 10]

 

This uses the variable part select syntax in Verilog, and is fully supported in any Verilog-2001 compliant synthesis tool or simulator (which all Xilinx products are).

 

The first example will work in SystemVerilog only. But Vivado fully supports SystemVerilog - you just need to turn on the SystemVerilog flag for the files in question (ISE does not support SystemVerilog, except through external synthesis and simulation tools).

 

Avrum

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Moderator
Moderator
10,082 Views
Registered: ‎07-01-2015

Hi @hphung,

 

I was telling something like the following Tcl coomand:

 

for {set i 0} {$i < 100} {incr i} {
puts "reg_$i"
}

 

This will print from reg_0 to reg_99 also you can change the statement inside puts to print the way you want to put into RTL.

 

Thanks,
Arpan

Thanks,
Arpan
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Observer
Observer
10,070 Views
Registered: ‎07-09-2014

Avrum, that is great, thanks! Hue

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Observer
Observer
10,067 Views
Registered: ‎07-09-2014

Arpan, got it, thanks for being so helpful. Hue

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