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azad
Visitor
Visitor
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Registered: ‎01-05-2021

Should reset signal be active high or low?

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Hi, 

I am working with a Kintex 7 Ultrascale plus FPGA. And we are trying to use the same code for FPGA and ASIC(as much similar as possible)

I wanted to ask if it is different to use ACTIVE HIGH or ACTIVE LOW reset?

I have found this in UG949 in 2015 :

"Control Signal Polarity (Active-High vs. Active-Low)
For high-fanout control signals like clock enables or resets, it is best to use active high in
the entire design. If a block operates with active low resets or clock enables, inverters get
added to the design and there is an associated timing penalty. It can restrict synthesis
options to flat or rebuilt to optimize the inverters or require the implementation of a
custom solution."

azad_0-1629111264201.png

But in newer version of UG949 this parts is removed.

So my question is if there is any drawback to use ACTIVE LOW reset in Kinex 7 Ultrascale plus?

Thank you

 

 

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avrumw
Expert
Expert
706 Views
Registered: ‎01-23-2009

Take a look at this post on active low resets.

We need to be clear, though, are you using "Kintex-7" or "Kintex UltraScale+" (there is no such thing as a "Kintex 7 UltraScale plus"). In Kintex-7 there is a penalty to using active low resets. In Kintex UltraScale+ that penalty no longer exists. So while I don't recommend using active low resets, if your ASIC code already uses them there is no need to change it in UltraScale/UltraScale+.

Avrum

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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@azad ,

I will only give you the short answer....

If you are doing ASIC prototyping work, then stick to what is implemented for the ASIC.

There are plenty of buffers inside any FPGA and most of the controls inside the FPGA also have the ability to invert the signal without adding a LUT. Routing, fan-out and polarity of reset signal for FPGA implementation should not be a major concern.

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Rmccarty
Explorer
Explorer
783 Views
Registered: ‎09-05-2020

Ultrascale+ parts have a built-in post configuration global reset and init. Unless you need some sort of reset that you need to actively control, you don't  need explicit reset pins. So far this has worked for me. The only reset in my designs is the clocking wizard which I tie to constant low.

seamusbleu
Voyager
Voyager
755 Views
Registered: ‎08-12-2008

My 2-cents.  I see no benefit, and some (albeit small) disadvantages to using low-active resets inside of an FPGA.  The negative logic just adds a little confusion, since basically all other signals in your design are going to be positive logic.  And the resets on the FPGA primitives are high-active, so why not just use a high-active reset?

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

Even if you use the same 'code' for FPGA and ASIC, the work flows are different, and what works in one may not work in the other, so I can't see the point of keeping the paralellism to that level.

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avrumw
Expert
Expert
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Registered: ‎01-23-2009

Take a look at this post on active low resets.

We need to be clear, though, are you using "Kintex-7" or "Kintex UltraScale+" (there is no such thing as a "Kintex 7 UltraScale plus"). In Kintex-7 there is a penalty to using active low resets. In Kintex UltraScale+ that penalty no longer exists. So while I don't recommend using active low resets, if your ASIC code already uses them there is no need to change it in UltraScale/UltraScale+.

Avrum

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

If there is no penalty in using active-low resets, why not recommended?

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seamusbleu
Voyager
Voyager
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Registered: ‎08-12-2008

To me, there is a small penalty in having to deal with negative logic - it just adds a small amount of confusion to the normal way of thinking about how logic is generated.  Now if there is some reason that low active reset makes sense for you, then go for it.  As has been discussed, the penalty - if any - is small.  But generally, what benefit is there to using low-active resets?  

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joancab
Teacher
Teacher
666 Views
Registered: ‎05-11-2015

I tend to use them (active low resets). The reason being the processor reset block generates them for peripherals so I don't have to drop an inverter (lazy me when designs have 1000s of LUTs)

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azad
Visitor
Visitor
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Registered: ‎01-05-2021

Hi Avrum, 

Sorry for my mistake, I am using Kintex UltraScale+. So as you mentioned there should be no penalty for using active low resets here. 

 

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richardhead
Scholar
Scholar
532 Views
Registered: ‎08-01-2012

Primarily, code should be written with ease of understanding in mind. Usually,  this will mean active high signals everywhere as it is generally easier to understand (as @avrumw already posted). Keeping things understanderble increases the likelihood people will keep your code after you've gone