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2,862 Views
Registered: ‎08-30-2017

Signal connected to multiple drivers

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multiple drivers.jpg

Hi,

I met this error message when synthesizing the design. The top level schematic can be found above. The bus Din[31:0] do connect to multiple source from different modules. However the outputs from different modules are controlled by individual enable pins which ensure that the drivers won't output simultaneously. How can I let the tool know about that? Should I change my code and how?

 

Thanks for the comments in advance!

 

BR,

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1 Solution

Accepted Solutions
Visitor iobass
Visitor
3,137 Views
Registered: ‎08-18-2017

Re: Signal connected to multiple drivers

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As @dpaul24 mentioned, the cheapest way (least logic, best timing) is to do this with a gated OR. (VHDL syntax)

 

  Din <= (Din_modA and enA) or (Din_modB and enB);
  -- add as many (Din and en) terms as you like, separated by ORs

To use a mux, as he suggested, requires summarizing the enables to a select line.  An array of enables is sometimes called "one-hot encoding" (especially for a state machine), while a mux select is sometimes called "binary encoding".  The select part would look something like the following.

 

  -- turn array of enables into a select, left gets priority
  Din_sel <= to_unsigned(find_leftmost(en_array, '1'), Din_sel'length);

  -- select from an array of Din values
  Din <= Din_array(to_integer(Din_sel));

Note that FPGAs are not very efficient for wide multiplexers.  A 4:1 MUX is a single level of logic for V6 and beyond.  Wider than that will be slower and larger.  (A little larger is still pretty efficient.  I commonly use 16:1 multiplexers with good timing/size results.)

 

Another option is to create a priority encoder.  An easy way is with an if-elsif chain.

  if '1' = en_modA then
    Din <= Din_modA;
  elsif '1' = en_modB then
    Din <= Din_modB;
  -- handle more modules with more elsif statements
  end if;

As far as I can see, these last two approaches are equivalent in behavior.  Your results may vary with any particular synthesizer.

 

One big question is what should happen if more than one enable is high at a time?  These solutions handle that case differently.  The OR solution (first) will give you garbage data on Din in this case -- the OR of the Din signal for the two modules.  The other solutions will pick one of the Din signals according to the priority you specify.  Depending on how many buses you need to combine, the size/latency costs can be significant.

 

These solutions also behave differently when no enable is active, but this behavior is usually unimportant.

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5 Replies
Scholar u4223374
Scholar
2,847 Views
Registered: ‎04-26-2015

Re: Signal connected to multiple drivers

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How can the pins not drive simultaneously? The logic in the FPGA is either high or low - it doesn't have a "floating" state. The only tristate-capable logic is on the external ports.

 

One option would be to put an OR gate in there, so that as long as one of them is zero the other one will get through.

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2,800 Views
Registered: ‎08-30-2017

Re: Signal connected to multiple drivers

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Thank you for your comments, u4223374

 

I think I can get your opinion about the internal logic status in FPGA.

But I am not sure if putting an OR gate there is correct for the design as you mentioned we don't know what the logic is on one side of Din when the other side is trying to drive the bus. The solution I think is to add another simple control logic.

 

 

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Scholar dpaul24
Scholar
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Registered: ‎08-07-2014

Re: Signal connected to multiple drivers

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Hi,

 

Well then add a MUX on the Din path, that would be safest.

Use the enable signal from the modules for the select signal of the MUX.

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Visitor iobass
Visitor
3,138 Views
Registered: ‎08-18-2017

Re: Signal connected to multiple drivers

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As @dpaul24 mentioned, the cheapest way (least logic, best timing) is to do this with a gated OR. (VHDL syntax)

 

  Din <= (Din_modA and enA) or (Din_modB and enB);
  -- add as many (Din and en) terms as you like, separated by ORs

To use a mux, as he suggested, requires summarizing the enables to a select line.  An array of enables is sometimes called "one-hot encoding" (especially for a state machine), while a mux select is sometimes called "binary encoding".  The select part would look something like the following.

 

  -- turn array of enables into a select, left gets priority
  Din_sel <= to_unsigned(find_leftmost(en_array, '1'), Din_sel'length);

  -- select from an array of Din values
  Din <= Din_array(to_integer(Din_sel));

Note that FPGAs are not very efficient for wide multiplexers.  A 4:1 MUX is a single level of logic for V6 and beyond.  Wider than that will be slower and larger.  (A little larger is still pretty efficient.  I commonly use 16:1 multiplexers with good timing/size results.)

 

Another option is to create a priority encoder.  An easy way is with an if-elsif chain.

  if '1' = en_modA then
    Din <= Din_modA;
  elsif '1' = en_modB then
    Din <= Din_modB;
  -- handle more modules with more elsif statements
  end if;

As far as I can see, these last two approaches are equivalent in behavior.  Your results may vary with any particular synthesizer.

 

One big question is what should happen if more than one enable is high at a time?  These solutions handle that case differently.  The OR solution (first) will give you garbage data on Din in this case -- the OR of the Din signal for the two modules.  The other solutions will pick one of the Din signals according to the priority you specify.  Depending on how many buses you need to combine, the size/latency costs can be significant.

 

These solutions also behave differently when no enable is active, but this behavior is usually unimportant.

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Contributor
Contributor
2,716 Views
Registered: ‎11-21-2016

Re: Signal connected to multiple drivers

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@wang_fan1982:

 

Vivado synthesis doesn't let you drive a signal from multiple sources. It shall give an error if you do so. Even though you are using enables, synthesis will map your entire RTL design in terms of gates and introduce wires in the netlist. This in turn will not look for when you're driving these enables. it's better to use a MUX between them. Normally when you flash the FPGA, it'll either show 'x' for reg or 'z' for wire. 

 

Simulation will work fine. But implementation and bitstream generation will fail.

 

Regards,

Suraj Kothari

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