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Visitor
Visitor
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Registered: ‎11-04-2013

Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

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i could not solve this warning 

 

WARNING:Xst:2999 - Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.
WARNING:Xst:3035 - Index value(s) does not match array range for signal <mem>, simulation mismatch.

 

 

my code is 

 

 

module rom_blocks_reverse_shifts (address , data , read_en );
input [6:0] address;
output [55:0] data;
input read_en;

reg [55:0] mem [0:77] ;


assign data = (read_en) ? mem[address] : 56'b0;

initial begin
$readmemb("C:/Users/kokomama/Desktop/msa/reverse_shifts.txt", mem,0);
end

endmodule

 

 

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Xilinx Employee
Xilinx Employee
8,718 Views
Registered: ‎07-11-2011

Re: Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

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Hi,

 

From the the warning messages and the piece of code this is what I understood/deduced.

 

WARNING:Xst:2999 - Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

---This says that mem is not dynamic and is tied to initial value which is correct as per your logic.

 

WARNING:Xst:3035 - Index value(s) does not match array range for signal <mem>, simulation mismatch

---This says that address [6:0] ranges to 128 is not the same as mem array range [0:77], which is also correct for your logic

 

 

I think you can ignore them and check if the read data is correct and the logic behaves correctly as the warnings are expected for your module.

 

Hope this helps.

 

 

Regards,

Vanitha

 

 

 

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Highlighted
Xilinx Employee
Xilinx Employee
8,719 Views
Registered: ‎07-11-2011

Re: Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

Jump to solution

Hi,

 

From the the warning messages and the piece of code this is what I understood/deduced.

 

WARNING:Xst:2999 - Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

---This says that mem is not dynamic and is tied to initial value which is correct as per your logic.

 

WARNING:Xst:3035 - Index value(s) does not match array range for signal <mem>, simulation mismatch

---This says that address [6:0] ranges to 128 is not the same as mem array range [0:77], which is also correct for your logic

 

 

I think you can ignore them and check if the read data is correct and the logic behaves correctly as the warnings are expected for your module.

 

Hope this helps.

 

 

Regards,

Vanitha

 

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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Highlighted
Visitor
Visitor
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Registered: ‎11-04-2013

Re: Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

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but this warning will make error when generate the program file
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Professor
Professor
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Registered: ‎08-14-2007

Re: Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

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Perhaps you could post the error message from "generate program file"?

-- Gabor
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Visitor
Visitor
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Registered: ‎11-04-2013

Re: Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

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when make generate program file for this code which use the above code these errors appear ?

 

 

 

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow
ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.

 

 

 

this code is 

 

 

 

module control_unit
(
input clk,
input [6:0] addreses_big_reg,
input valid_out_big_reg,
input rst_main_and_ctrlunt, //One active low cycle with neg edge reset from the main decoder
input end_frame, //From mem_and_msa
input validout_write,
input s2p_validout, //From serial to parallel
input p2s_validout, //From parallel to serial
input valid_out_checknode, //From check node
input [7:0] no_iterations,


output reg [2:0] Nvn, //From Rom Nvn
output reg first_it, //High cycle at first itreration
output reg first_it_mux_mem,
output reg dummy_init, //High cycle at sub-iterations 62,64,66
output [6:0] updates_mem_addrs, //From sub-iteration counter
output reg [1:0] up_down,
output reg [6:0] shift_p0, //From Rom shifts
output reg [6:0] shift_p1, //From Rom shifts
output reg [6:0] shift_r0, //From Rom reverse shifts
output reg [6:0] shift_r1, //From Rom reverse shifts
output reg [6:0] addrs_mem_VNs, //From big reg then Rom addresses
output reg rd, //Read signal
output reg wr, //Write signal
output reg rst,
output reg validin_mem_read, //For reading
output reg valid_out_ctrl_unt,
output reg read_Ldpc_output //High cycle after all iterations finished
);

reg [7:0] iteration_number; //Current number of iteration
reg [6:0] sub_iteration_number; //Current number of sub-iteration
reg [6:0] cycles_counter;
reg [1:0] cycles_counter_1;
reg [2:0] read_counter;
reg [2:0] write_counter;
wire [55:0] addrs_rom;
wire [55:0] shifts_rom;
wire [55:0] reverse_shifts_rom;
wire [2:0] Nvn_rom;
reg read_Nvn;
reg read_addrs;
reg read_shifts;
reg read_reverse_shifts;
reg flag1;//end_frame==1 & sync read counter
reg flag2;//p2s_validout == 1,flag7==0
reg flag3;//flag4==0
reg flag4;//High cycle at sub-iterations 62,64,66
reg flag5;//cycles_counter_1 == 3'b010
reg flag6;//flag7==0, p2s_validout=1
reg flag7;//(iteration_number == (no_iterations + 8'b00000001)) && (wr == 0)
reg [5:0] i;

rom_Nvn No_vn_rom (
.address(sub_iteration_number),
.data(Nvn_rom),
.read_en(read_Nvn)
);

rom_blocks_addresses addrs_blocks_rom (
.address(sub_iteration_number),
.data(addrs_rom),
.read_en(read_addrs)
);

rom_blocks_shifts shfts_rom (
.address(sub_iteration_number),
.data(shifts_rom),
.read_en(read_shifts)
);

rom_blocks_reverse_shifts reverse_shfts_rom (
.address(sub_iteration_number),
.data(reverse_shifts_rom),
.read_en(read_reverse_shifts)
);

assign updates_mem_addrs = sub_iteration_number;

always@(posedge clk or negedge rst_main_and_ctrlunt)
begin
if(!rst_main_and_ctrlunt)
begin
iteration_number=1;
sub_iteration_number=0;
//
cycles_counter=0;
cycles_counter_1=0;
read_counter=0;
write_counter=0;
//
read_Nvn=1;
read_addrs=1;
read_shifts=1;
read_reverse_shifts=1;
//
first_it=0;
dummy_init=0;
up_down=2'b10;
rst=1;
rd=0;
wr=0;
validin_mem_read=0;
read_Ldpc_output=0;
first_it_mux_mem=0;
flag1=0;
flag2=0;
flag3=0;
flag4=0;
flag5=0;
flag6=0;
flag7=0;
i=0;
valid_out_ctrl_unt=0;
end
else
begin//1
if(iteration_number == 1)
begin//2
if(sub_iteration_number == 0)
begin//3
if(cycles_counter <7'b1001110)///////////////
begin
first_it=1;
rst=1;//rst internal mem in c-node updates_mem = 0;signs_mem = 0;
cycles_counter=cycles_counter+7'b0000001;
end
else
begin
if(cycles_counter == 7'b1001110)
begin
first_it=0;
rst=0;
Nvn=Nvn_rom;
cycles_counter=cycles_counter+7'b0000001;
end
else
begin//
if(cycles_counter == 7'b1001111)
begin
rst=1;
cycles_counter=cycles_counter+7'b0000001;
end
end//
end ////////////////////


if(valid_out_big_reg == 1)//make validin_mem_write=1 inside oring
begin
wr=1;
first_it_mux_mem=1;//dummy init must =0
addrs_mem_VNs = addreses_big_reg;
end
else
begin
wr=0;
first_it_mux_mem=0;
end


if(end_frame == 1)
begin
first_it_mux_mem=0;
wr=0;
validin_mem_read=1;
flag1=1;
rd=1;
addrs_mem_VNs=addrs_rom[(3'b110-read_counter)*8+:8];
end

end//3
end//2

if(((validout_write == 0) && (sub_iteration_number <= 7'b1001101)
&& (flag2==1) && (flag4 == 0)) || ((flag3 == 1) && (flag4 == 0)) || (flag5 == 1))

begin////////
if(cycles_counter_1 == 2'b00)
begin///-
if(flag5 == 0)
begin
sub_iteration_number=sub_iteration_number+7'b00000001;
end
if(((sub_iteration_number == 7'b0111110) || (sub_iteration_number == 7'b1000000) || (sub_iteration_number == 7'b1000010)) && (flag5 == 0))
begin
flag4=1;//dummy_init => High cycle at sub-iterations 62,64,66
end
if(flag4 ==0)
begin
flag3=1;
cycles_counter_1=cycles_counter_1+2'b01;
end
end///-
else
begin
if(cycles_counter_1 == 2'b01)
begin
rst=0;
cycles_counter_1=cycles_counter_1+2'b01;
end
else
begin
if(cycles_counter_1 == 2'b10)
begin
Nvn=Nvn_rom;
validin_mem_read=1;
rst=1;
flag1=1;
rd=1;
flag2=0;
addrs_mem_VNs=addrs_rom[(3'b110-read_counter)*8+:8];
cycles_counter_1=cycles_counter_1+2'b01;
end
end
end
end///////
if(flag4 == 1)
begin//(flag4 == 1)
if(cycles_counter_1 == 2'b00)
begin
cycles_counter_1=cycles_counter_1+2'b01;
end
else
begin
if(cycles_counter_1 == 2'b01)
begin
dummy_init=1;
wr=1;
rst=0;
addrs_mem_VNs=8'b10000111;
cycles_counter_1=cycles_counter_1+2'b01;
end
else
begin
if(cycles_counter_1 == 2'b10)
begin
dummy_init=0;
wr=0;
rst=1;
flag5=1;
flag4=0;
cycles_counter_1=1; //It may be set to be 0 for more safety when reading from memory after writing
end
end
end
end//(flag4 == 1)
if((read_counter == Nvn_rom) && (read_counter != 0))
begin
validin_mem_read=0;
flag1=0;
flag5=0;
rd=0;
read_counter=0;
end
if(flag1 == 1)
begin
addrs_mem_VNs=addrs_rom[(3'b110-read_counter)*8+:8];
read_counter=read_counter+3'b001;
end
if(valid_out_checknode == 1)//occur after read_counter == Nvn_rom
begin
shift_p0=shifts_rom[(3'b110-read_counter)*7+:7];
shift_p1=shifts_rom[(3'b101-read_counter)*7+:7];
read_counter=read_counter+3'b010;
end
if(s2p_validout == 1)//occur after read_counter == Nvn_rom
begin
shift_r0=reverse_shifts_rom[(3'b110-read_counter)*7+:7];
shift_r1=reverse_shifts_rom[(3'b101-read_counter)*7+:7];
read_counter=read_counter+3'b010;
end
if(p2s_validout == 1)
begin///
if(flag7 == 0)
begin
flag6=1;
wr=1;
addrs_mem_VNs=addrs_rom[(3'b110-write_counter)*8+:8];
write_counter=write_counter+3'b001;
flag2=1;
flag3=0;
cycles_counter_1=0; //A signal that synchrounized with negative edge of valid_out_write
if((sub_iteration_number == 7'b1001101) && (iteration_number <= no_iterations))
begin
sub_iteration_number=0;
iteration_number=iteration_number+1;
end
end
end
else
begin
if(flag6 == 1)
begin
wr=0;
write_counter=0;
end
end///
if((s2p_validout == 0) && (valid_out_checknode == 0) && (flag1 == 0))
begin
read_counter=0;
end
if((iteration_number == (no_iterations + 8'b00000001)) && (wr == 0))
begin//////
flag7=1;
if(i<60)//7200/120
begin
rd=1;
addrs_mem_VNs=i;
read_Ldpc_output=1;
validin_mem_read=1;
i=i+1;
valid_out_ctrl_unt=1;
/*if(i == 3)
begin
valid_out_ctrl_unt=1;
end*/
end
else
begin
rd=0;
validin_mem_read=0;
valid_out_ctrl_unt=0;
read_Ldpc_output=0;

/*if((i >= 60) && (i <= 61))
begin
i=i+1;
rd=0;
validin_mem_read=0;
end
else
begin
if(i > 61)
begin
valid_out_ctrl_unt=0;
read_Ldpc_output=0;
end
end */
end
end//////
end //1
end//always
endmodule

 

please help me to solve it 

 

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Professor
Professor
6,680 Views
Registered: ‎08-14-2007

Re: Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

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The bitgen errors have nothing to do with the source code.  You need to make sure that all I/O pins are located (UCF file has a LOC constraint) and have an I/O Standard defined.  This is not optional for the 7-series parts.  Older parts allowed un-located pins and "default" I/O standards.

 

see AR #51813

-- Gabor
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