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Registered: ‎10-22-2019

Simple Dual Port in Write First mode with Synthesis constructs

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Hello All,

I am trying to implement a write first Simple Dual Port in Write First mode and High Performance mode.

The code present in Language templates from Vivado (VHDL, Synthesis constructs) seems to infer Read First mode and does not show how to implement Wirte first mode

 

process(<clka>)
begin
    if(<clka>'event and <clka> = '1') then
        if(<wea> = '1') then
            <ram_name>(to_integer(unsigned(<addra>))) <= <dina>;
        end if;
        if(<enb> = '1') then
            <ram_data> <= <ram_name>(to_integer(unsigned(<addrb>)));
        end if;
    end if;
end process;

By changing the code like so, a complex logic is infered around the RAM instead of using a write first ram block.

process(<clka>)
begin
    if(<clka>'event and <clka> = '1') then
        if(<wea> = '1') then
            <ram_name>(to_integer(unsigned(<addra>))) <= <dina>;
        end if;
        if(<enb> = '1') then
        	if(<wea> = '1' and <addra> = <addrb>) then
        		<ram_data> <= <dina>;
    		else
	            <ram_data> <= <ram_name>(to_integer(unsigned(<addrb>)));
            end if;
        end if;
    end if;
end process;

My question is how to infer a Simple Dual Port RAM in Write First mode with VHDL Synthesis constructs

Thank you for your help

Victor

 

 

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Accepted Solutions
Highlighted
Scholar
Scholar
542 Views
Registered: ‎08-01-2012

For write first, use a shared variable rather than signal for the ram storage.

Note. Technically, shared variables need to be a protected type from VHDL 2002 onwards. If Vivado throws an error about this, you'll have to drop down to VHDL 1993. You may need to use the XPM blocks for write first if you have to use VHDL 2002+

I would argue though that if you need a specific write/read first behaviour, you have a design issue. Reading/writing from the same address should be avoided (then you dont care about the mode).

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2 Replies
Highlighted
Scholar
Scholar
543 Views
Registered: ‎08-01-2012

For write first, use a shared variable rather than signal for the ram storage.

Note. Technically, shared variables need to be a protected type from VHDL 2002 onwards. If Vivado throws an error about this, you'll have to drop down to VHDL 1993. You may need to use the XPM blocks for write first if you have to use VHDL 2002+

I would argue though that if you need a specific write/read first behaviour, you have a design issue. Reading/writing from the same address should be avoided (then you dont care about the mode).

View solution in original post

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Highlighted
530 Views
Registered: ‎10-22-2019
Thank you,

I modified the design to avoid the collision

Victor
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