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Visitor
Visitor
7,391 Views
Registered: ‎06-22-2016

Simple UART Interface

Hi all,

 

I am trying to implement a very simple uart. Terminal output is inconsistent and I can't seem to spot the error. Code below;

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart is
Port ( clk	: in STD_LOGIC;
		 tx : out STD_LOGIC);
end uart ;
architecture Behavioral of uart is
signal counter : unsigned ( 11 downto 0) := (others => '0');
signal shift : std_logic_vector(39 downto 0) := x"48454c4c4f";
begin
   tx  <= shift(39);	
process(clk)
   begin
	if rising_edge(clk) then
		if counter = 5 then
			counter <= (others => '0');
			shift <= shift(38 downto 0) & shift(39);
		else
			counter <= counter+1;
		end if;
	end if;
   end process;
end Behavioral;

Any ideas ?

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10 Replies
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Teacher
Teacher
7,382 Views
Registered: ‎03-31-2012

Re: Simple UART Interface

what speed is your clock?

 

assuming you are running in 8N1 mode, every byte needs 1 start bit, 8 data bits and 1 stop bit. Are you supplying those in your code?

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Visitor
Visitor
7,372 Views
Registered: ‎06-22-2016

Re: Simple UART Interface

clock is 50Mhz I am using 9600 baud rate 8n1. new code below still not working ;

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart is
Port ( clk	: in STD_LOGIC;
		 tx : out STD_LOGIC);
end uart ;
architecture Behavioral of uart is
signal counter : unsigned ( 12 downto 0) := (others => '0'); 
signal shift : std_logic_vector(7 downto 0) := "00000001";
begin
   tx  <= shift(7);	
process(clk)
   begin
	if rising_edge(clk) then
		if counter = 5206 then
			counter <= (others => '0');
			shift <= shift(6 downto 0) & shift(7);
		else
			counter <= counter+1;
		end if;
	end if;
   end process;
end Behavioral;
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Teacher
Teacher
7,364 Views
Registered: ‎03-31-2012

Re: Simple UART Interface

the counter max is 5207 but it doesn't matter much. I think the main issue is that you are still generating 8 bits. You should be generating 10 bits (Start, 8 data, stop).
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Visitor
Visitor
7,363 Views
Registered: ‎06-22-2016

Re: Simple UART Interface

same behavior, nothing is on the terminal.

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Teacher
Teacher
7,359 Views
Registered: ‎03-31-2012

Re: Simple UART Interface

what do you have as the middle 8 bits? put a visible ascii char there.

 

of course this assumes you did the tx pin assignment properly. 

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Visitor
Visitor
7,356 Views
Registered: ‎06-22-2016

Re: Simple UART Interface

I have '00000001' as middle 8;

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart is
Port ( clk	: in STD_LOGIC;
		 tx : out STD_LOGIC);
end uart ;
architecture Behavioral of uart is
signal counter : unsigned ( 12 downto 0) := (others => '0'); 
signal shift : std_logic_vector(9 downto 0) := "1000000011";
begin
   tx  <= shift(9);	
process(clk)
   begin
	if rising_edge(clk) then
		if counter = 5206 then
			counter <= (others => '0');
			shift <= shift(8 downto 0) & shift(9);
		else
			counter <= counter+1;
		end if;
	end if;
   end process;
end Behavioral;

It can be seen from the code as well.

 

 

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Teacher
Teacher
7,354 Views
Registered: ‎03-31-2012

Re: Simple UART Interface

That's not going to print anything. Try 0x41 has the middle 8 bits.
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Visitor
Visitor
7,348 Views
Registered: ‎06-22-2016

Re: Simple UART Interface

signal shift : std_logic_vector(9 downto 0) := "1000000011";

Are you suggesting to type hex to logic_vector ?

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Teacher
Teacher
7,345 Views
Registered: ‎03-31-2012

Re: Simple UART Interface

try "0010000011" as your constant.

And check your pin assignment.
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Visitor
Visitor
5,483 Views
Registered: ‎06-22-2016

Re: Simple UART Interface

There is output but it's all weird characters ?

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