02-06-2017 10:23 AM
I have a snippet of code for an adder that synthesizes in ISE XST (14.7), but fails in Vivado synthesis (2016.1):
ADDER: process (SIG_Vector1, SIG_Vector2, ADDX, SIG3)
if (ADDX = '1') then
-- SUMD_TEMP is (0 to 16) std_logic_vector.
SUMD_TEMP <= SIG_Vector1 + SIG_Vector2 + SIG3;
-- std_logic_Vector(0 to 15) + std_logic_vector(0 to 15) + std_logic;
SUMD_TEMP <= SIG_Vector1 - SIG_Vector2 - (not SIG3)
end process ADDER;
SUMD <= SUMD_TEMP(1 to 16);
-- SUMD is (0 to 15)
Here is the error output from Vivado:
"[Synth 8-690] width mismatch in assignment; target has 17bits, source has 16bits [adder.vhd:126]" (failing line is SUMD_TEMP <= SIG_Vector1 + SIG_Vector2 + SIG3; )
I am kind of confused as to why it would error out here in Vivado, but not ISE?
02-06-2017 01:32 PM
@jechambe-koe in vhdl you cannot assign vectors of different sizes to Vivado is right here. Most probably ISE had a weakness in this area and they fixed it in Vivado.
02-06-2017 01:43 PM
But, that means that Vivado is not doing the ADD operation. When you add two 16bit values, you need a 17bit vector to store the results "1111 1111 1111 1111" (0xFFFF) + "1111 1111 1111 1111" (0xFFFF) + "1" (0x1) = "1 1111 1111 1111 1111" (0x1 FFFF) (17 bits).
This is something that ISE XST would do just fine, and if you didn't have a 17bit register, you would get an error that the results need to be a 17bit vector.
I guess if you can't do the basic addition I posted in the example, then what is proper way to do basic std_logic_vector addition in Vivado?
02-06-2017 01:56 PM
@jechambe-koe if you want to make sure you are getting a 17 bit result, you need to (sign or zero) extend the input variables.
ie if your inputs are unsigned, saying c <= '0' & a + '0' & b; should get you what you want.