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Visitor splee
Visitor
8,203 Views
Registered: ‎09-07-2011

Simple code.. pls help

Hi,

I am a beginner of VHDL.

I wrote a simple code below. The compiler warns me that 'b' should be in the sensitivity list. Why is this so?

Would the synthesis be different if I include b in the sensitivity list?

 

entity simpleBuffer is
    Port ( a : in  STD_LOGIC;
           c : out  STD_LOGIC);
end simpleBuffer;

architecture Behavioral of simpleBuffer is
signal b    : STD_LOGIC;
begin
    process (a)
    begin
            b <= a;
            c <= b;
    end process;
end Behavioral;

 

 

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10 Replies
Highlighted
Historian
Historian
8,194 Views
Registered: ‎02-25-2008

Re: Simple code.. pls help


@splee wrote:

Hi,

I am a beginner of VHDL.

I wrote a simple code below. The compiler warns me that 'b' should be in the sensitivity list. Why is this so?

Would the synthesis be different if I include b in the sensitivity list?

 

entity simpleBuffer is
    Port ( a : in  STD_LOGIC;
           c : out  STD_LOGIC);
end simpleBuffer;

architecture Behavioral of simpleBuffer is
signal b    : STD_LOGIC;
begin
    process (a)
    begin
            b <= a;
            c <= b;
    end process;
end Behavioral;

 

 


If you're a VHDL newbie, you should stop what you're doing and buy a copy of Ashenden's "Designer's Guide To VHDL." Everything you are asking is answered in that nice book.

----------------------------Yes, I do this for a living.
Tags (1)
Instructor
Instructor
8,188 Views
Registered: ‎08-14-2007

Re: Simple code.. pls help

The simple answer to the question is no, synthesis will not be different if you add b to

the sensitivity list.  On the other hand simulation may be different.  I'm not fluent enough

in VHDL to know whether the assignment "c <= b" takes the value of b before or after

the assignment "b <= a" above it.  If this were Verilog, the previous value of b would be

assigned to c.  So in effect the simulation would behave differently if you add b to

the sensitivity list.

 

The reason you get a warning, is that for synthesis all right-hand-side variables

are assumed to be in the sensitivity list, so if any are missing you have the

potential for a mis-match between simulated and synthesized behavior.  As I

said it isn't clear to me whether this is one of those cases, but you will get the

warning regardless.

 

Obviously since you always simulate code before synthesis, you can see for

yourself whether the simulation behavior changes with the addition of b.

 

-- Gabor

-- Gabor
Visitor splee
Visitor
8,174 Views
Registered: ‎09-07-2011

Re: Simple code.. pls help

Hi Bassman59,

 

Now I understand that:

- all signals on the right hand side of the "<=" must be in the sensitivity list

- synthesis tools ignore sensitivity list, anyway

 

My one question would be:

In a process statement, a signal only gets its assigned value after the process suspends, eg. in Behav1, b only gets the value of a after the process suspends. Why would a synthesis tool make it such complicated? I mean, why can't a signal  get the value immediately, just like variable and like in C program? What's the point of making things difficult?

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Teacher eteam00
Teacher
8,170 Views
Registered: ‎07-21-2009

Re: Simple code.. pls help

why can't a signal  get the value immediately, just like variable and like in C program? What's the point of making things difficult?

 

Here is an excellent explanation of blocking and non-blocking assignments.  It is written for Verilog, but the same principles and similar constructs apply to VHDL.

 

                                 assignments

language   blocking  non-blocking

Verilog       =         <=

VHDL         :=         <=

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Advisor eilert
Advisor
8,148 Views
Registered: ‎08-14-2007

Re: Simple code.. pls help

Hi all,

the assignment comparision table has one little flaw. (But it is intended for learning verilog, so it is OK)

The := assignment in VHDL is for variables, and variable values can not leave the process, they are local.

 

Still, a good mixture of using variables and signals can be applied to splee's problem:

 

architecture Behavioral of simpleBuffer is
-- signal b    : STD_LOGIC; -- not necessary, since it will only be used in the process
begin
    process (a)

      variable b    : STD_LOGIC;
    begin
            b := a;
            c <= b;
    end process;
end Behavioral;

 

For simulation:

Now the process gets triggered by changes on signal/port a. Variable b is updated immediately and then assigned to signal/port c.

I may mention that some simulators have difficulties at showing variable values. Sometimes these are even optimized away. Be aware of this when simulating.

 

For synthesis, there is no difference.

 

____

 

About splee's question: "What's the point of making things difficult?"

The language isn't making things difficult. It's a computer language and so it does just what you tell it to do.

Also you are describing hardware, so the language needs a way to model hardware behavior.

That's why there are signals with their special behavior.

Signals and sensitivity lists together are a very simple way to deal with the problem of concurrency.

All processes (and concurrent assignments and instances) are working concurrently just like hardware does, and the simulator needs to handle this in a sequential way, since it runs on a CPU.

 

Have a nice synthesis

  Eilert

Teacher eteam00
Teacher
8,144 Views
Registered: ‎07-21-2009

Re: Simple code.. pls help

Thanks for the help, Eilert.  I clearly know too little about VHDL to be explaining it to someone else.

 

Good explanation!

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher rcingham
Teacher
8,137 Views
Registered: ‎09-09-2010

Re: Simple code.. pls help

"What's the point of making things difficult?"

To keep our pay rates moderately high...
;-)

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Instructor
Instructor
8,133 Views
Registered: ‎08-14-2007

Re: Simple code.. pls help

Actually if the language is difficult, synthesis takes the easy way out by ignoring the

sensitivity list.  However, the list was not intended to make things difficult.  In fact it was

to make simulation simpler because the simulator is told which events need to

wake the process.  Some day XST will support the 2008 extensions to VHDL and

you will be able to use the "all" keyword to automatically place all right-hand side

signals in the sensitivity list.

 

-- Gabor

 

Also you might want to look into the history of VHDL and Verilog.  Neither language

was originally intended for synthesis.  That came later.  And it's still maturing, in

that synthesizers are continuing to add more of the language to their list of

synthesizable constructs.

-- Gabor
Explorer
Explorer
8,124 Views
Registered: ‎08-14-2007

Re: Simple code.. pls help

RE: making things difficult:

Because if it updated immediately, and you read it in another process, you'd get race conditions, just like in Verilog if you use the wrong type of assignment. In VHDL you *can't* make that mistake as anything you use to communicate with another process is a signal which has (by definition) non-blocking semantics. http://www.sigasi.com/content/vhdls-crown-jewel
Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
Historian
Historian
2,378 Views
Registered: ‎02-25-2008

Re: Simple code.. pls help


@splee wrote:

Hi Bassman59,

 

Now I understand that:

- all signals on the right hand side of the "<=" must be in the sensitivity list

- synthesis tools ignore sensitivity list, anyway

 

My one question would be:

In a process statement, a signal only gets its assigned value after the process suspends, eg. in Behav1, b only gets the value of a after the process suspends. Why would a synthesis tool make it such complicated? I mean, why can't a signal  get the value immediately, just like variable and like in C program? What's the point of making things difficult?


Why is it so complicated? It's not that the synthesis tool makes it complicated -- this concept is for simulation.

 

And it is intended to model real hardware. The scheduling of assignments and delta time concepts are one way of making sure of this. The point is that everything on the right-hand side of an assignment has to "settle" before the assignment can be completed.

----------------------------Yes, I do this for a living.
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