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reginaldstjohn
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Registered: ‎03-12-2018

(Solved) Input port signal being deleted in Synthesis

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We have a fairly simple design with a SPI (CS, SpiClk, MISO) interface into our FPGA (Artix7).  We simulate and get everything working. When we Synthesize Vivado removes the MISO signal from the design.  It is like it is getting optimized out but there is no warning or information that it is being removed. If we look at the schematic the port shows up but not connected to anything.  There are no nets in the net list that are connected to it.

We have tried creating a signal and then specifying the "keep" attribute but it still goes away.

I know there are more details that would probably help but we are stumped at this time. Any suggestions?

 

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anusheel
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Registered: ‎07-21-2014

Hi @reginaldstjohn ,

Please use synth_design command with "-debug_log" to get debug log for 2020.x release. Also, please check the elaborated design to verify the connectivity. 
Also, I am assuming the input port is not removed from the design but the internal connection to the input port is removed. 


Thanks
Anusheel 

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anusheel
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Registered: ‎07-21-2014

Hi @reginaldstjohn ,

Please use synth_design command with "-debug_log" to get debug log for 2020.x release. Also, please check the elaborated design to verify the connectivity. 
Also, I am assuming the input port is not removed from the design but the internal connection to the input port is removed. 


Thanks
Anusheel 

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reginaldstjohn
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Registered: ‎03-12-2018

Anusheel,

Thank you for your response. We ran the synth_design -debug_log and that was helpful. We did notice that in the elaborated design the signal appears to be connected to another module but if you look inside that module it doesn't go anywhere. The output of the synth_design now does say that that signal, along with a couple of others from a CDC module are either unconnected or has no load. As an aside, The CDC modules are Xilinx xmp modules who's documentation is very confusing especially regarding the resets.

---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3917] design Top has port o_ErrorInterrupt driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_EIMWait driven by constant 1
WARNING: [Synth 8-3917] design Top has port o_SenNum[1] driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_SenNum[0] driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_FPGA_TP12 driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_FPGA_TP8 driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_FPGA_TP11 driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_FPGA_TP10 driven by constant 0
WARNING: [Synth 8-3917] design Top has port o_FPGA_TP7 driven by constant 0
WARNING: [Synth 8-7129] Port src_clk in module xpm_cdc_single is either unconnected or has no load
WARNING: [Synth 8-7129] Port src_rst in module xpm_cdc_pulse is either unconnected or has no load
WARNING: [Synth 8-7129] Port dest_rst in module xpm_cdc_pulse is either unconnected or has no load
WARNING: [Synth 8-7129] Port slave1_miso in module Top is either unconnected or has no load
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\spi1/m_axis_tvalid_reg )
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[0]' (FDRE) to 'spi1/m_axis_tdata_reg[1]'
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[1]' (FDRE) to 'spi1/m_axis_tdata_reg[2]'
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[2]' (FDRE) to 'spi1/m_axis_tdata_reg[3]'
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[3]' (FDRE) to 'spi1/m_axis_tdata_reg[4]'
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[4]' (FDRE) to 'spi1/m_axis_tdata_reg[5]'
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[5]' (FDRE) to 'spi1/m_axis_tdata_reg[6]'
INFO: [Synth 8-3886] merging instance 'spi1/m_axis_tdata_reg[6]' (FDRE) to 'spi1/m_axis_tdata_reg[7]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\spi1/m_axis_tdata_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Fifo1/r_ReadPtr0_inferred /\Fifo1/r_ReadPtr_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Fifo1/r_ReadPtr0_inferred /\Fifo1/r_ReadPtr_reg[1] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2496.781 ; gain = 0.000

However, We cannot for the life of us figure out why that would be.

The miso signal is is defined in the pin constraints file.

The TopLevel.vhd file has it as an input port

The input port goes into a SpiModule entity as an input

The input is used to feed a shift register to deserialize the miso bits

Again, when we pre-sythesis simulate the simulation works as expected, even with the miso as a constant value.

Could this be a problem that since the xpm cdc modules are not synthesizing correctly that the module is not seeing a clock and therefore thinking that the miso signal never gets uses? If this is true I would expect many other signals to be "unconnected" as well.

Any guidance would be helpful at this time.  

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reginaldstjohn
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Registered: ‎03-12-2018

We found the problem. We had an integer that was not the correct range and therefore would not satisfy some conditions in our state machine. This then caused chunks of code to be removed.  Dumb mistake.

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