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ravics
Observer
Observer
6,811 Views
Registered: ‎08-26-2010

Spectral Averaging VHDL

How can I perform spectral averaging using VHDL? I'm getting output from Xilinx FFT IP Core & need to average several successive spectra? What is the methodology for Spectral Averaging?

Any sample code of averaging for efficient synthesis would help.

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eteam00
Instructor
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Registered: ‎07-21-2009

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rcingham
Teacher
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Registered: ‎09-09-2010

Do you just want an arithmetic average every N outputs?
Or a rolling average?
Or some sort of IIR effect?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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martinthompson
Explorer
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Registered: ‎08-14-2007

If you really want to average (ie find the mean) the spectrum over several iterations, there's not much you can do but add up the values and divide by the number of iterations:

 

 

Create a large RAM block with one bin per FFT bin.

 

After each FFT, iterate over the bins, reading the current value from RAM, adding the latest value and storing it back.   Call this RAM block the "bin accumulators"


Also keep track of how many times you've done this.  Call this counter the "stored count"

 

When it comes to readout, divide each of the bin accumulators by the stored count and send the result on.

 

Keep your number of iterations a power of 2 to make the divider into a trivial shift.

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
ravics
Observer
Observer
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Registered: ‎08-26-2010

FFT output is stored in Block Memory Generator IP. How access memory elements according to address? FFT output width is 16 bit with 1024 NFFT, block ram word length is 16 bit with 1024 depth.

 

 

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joelby
Advisor
Advisor
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Registered: ‎10-05-2010

Your question is a little vague. You can access BRAM elements by address - just feed an address in to an address port.

 

The FFT core has nice index signals, XN_INDEX and XK_INDEX, which you can use to interface with your BRAM's address port. When I last implemented an FFT magnitude averaging scheme, I used the optional three cycle input data timing delay to give myself plenty of time to read the previous value out and add it to the new value (the data sheet claims that this shouldn't be necessary 'in many cases')

ravics
Observer
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Registered: ‎08-26-2010

Can SRL be used for std_logic_vector division?

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joelby
Advisor
Advisor
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Registered: ‎10-05-2010

I can't really think how you'd sensibly accomplish a division with a SRL. They operate on a single bit at a time and the FFT outputs entire words. Power of two division can easily be done with LUTs:

 

reg [15:0] number;
wire [7:0] divided_by_256;

assign divided_by_256[7:0] = number[15:8];

If you fed a number into a SRL, LSB first, and then changed the length (using dynamic shift mode) you could produce a programmable power of two divider, sort of. But you might need a state machine to drive it, and it'd have considerable latency.