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Observer
Observer
7,258 Views
Registered: ‎07-04-2014

Static var inside a function

Hello,

 

I need your help about the scope of a static ver (a memory) inside a function.

 

 

I have two modules:

 

module moduleWriter(input clock, input reset, input enabled);
module moduleReader(input clock, input reset, input enabled, output var[7:0] value);

 

 

 

Both of them uses a function which has a static variable inside:

 

function [7:0] memoryFunc(var opWrite, var[31:0] address, var[7:0] value = 0);

    static var [7:0] ram [0:1023]; 

    if (opWrite)
    begin
        ram[address] = value;
        return value;
    end
    else
        return ram[address];

endfunction

 

The ram variable wants to be a buffer written from several section of code.

In the attached example I aspect to have in output leds the value 30, but I get always 0. It seems the value rams is iniziled every time I called memryFunc.

 

Do you have an idea about what is wrong? I am using SystemVerilog and Vivado 2015.4, simulating a VC707 board.

Attached you can find a self consistent example.

 

Thank you

Michele Renda

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Observer
Observer
7,246 Views
Registered: ‎07-04-2014

I think I found the possible cause:

SystemVerilog has static and automatic tasks and functions. Vivado synthesis treats all tasks and functions as automatic.

http://www.xilinx.com/support/answers/51533.html

 

Anyone has a suggestion how can I workaround this? The other solution that comes to my mind is to pass the memory by ref, but Vivado System Verilog dialect does not support this too.

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Observer
Observer
7,224 Views
Registered: ‎07-04-2014

With the help of someone a bit more expert I found the right way to implement what I wanted. I post here the results to help other people with the same problem.

 

Regards